Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/armv7/psci.S
From: Ian Campbell
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
Signed-off-by: Ian Campbell
Signed-off-by: Jan Kiszka
---
arch/arm/include/asm/arch-tegra124/mc.h | 35 +++--
1 file ch
Changes in v3:
- use memory node adjustment for RAM carveout instead of reservation
- style fixes
Find patches also under
https://github.com/siemens/u-boot/tree/jetson-tk1-v3
Jan
CC: Ian Campbell
Ian Campbell (3):
tegra124: Add more registers to struct mc_ctlr
jetson-tk1: Add PSCI conf
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/armv7/psci.S | 19 +++
arch/arm/cpu/armv7/sunxi/psci.S | 21 ++---
2 files changed, 21 insertions(+), 19 del
We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to
happen for all cores.
Fixing this resolves problems of KVM with emulating the generic
timer/counter.
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/armv7/tegra-common/psci.S | 13 +
1 file changed, 13 insertions(+)
This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/armv7/psci.S | 14 ++
arch/arm/cpu/armv7/sunxi/psci.S | 17 +++--
2 files changed, 21 insertions(+), 10 deletions(-)
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/armv7/psci.S | 8 ++--
arch/arm/cpu/armv7/sunx
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this version for turning CPUs on and
off was proposed by Thierry Reding in
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881.
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memor
Will be used for unpowergating CPUs.
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/tegra-common/powergate.c | 2 +-
arch/arm/include/asm/arch-tegra/powergate.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/tegra-common/powergate.c
b/arch/arm/cpu/tegra-comm
This function will be used to initialize CPU power management for Tegra
SOCs. For now it does nothing.
Signed-off-by: Jan Kiszka
---
arch/arm/include/asm/arch-tegra/ap.h | 5 +
board/nvidia/common/board.c | 4
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/
From: Ian Campbell
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.
Signed-off-by: Ian Campbell
Signed-off-by: Jan Kiszka
---
arch/arm/cpu/armv7/tegra12
From: Ian Campbell
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.
At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, whi
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
> Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
> Aigo M60/M608/M606 tablets.
>
> Signed-off-by: Hans de Goede
All 4 patches: Acked-by: Ian Campbell
I a couple of small comments on this one, which you can eithe
This patch adds "iRAM, CPU state and low power" configs
which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x0202+CPUID*4).
This is a part of iROM logic. Rest other flags are being
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core s
This patch series introduces changes for booting secondary CPUs
on Exynos5420 and Exynos5800.
Changes since v2:
- Patch 7 & 8 : Replaced #ifdef and #ifndef -> if(proid_is_soc()).
- Patch 11 : Removed #ifdef from enum definition.
Changes since v1:
- Added Reviewed-by & Test
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a rece
This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the log
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat
Reviewed-by: Simon Glass
Tested-b
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay Sara
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switc
From: Doug Anderson
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't ta
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do
Until yet usb_**_msg() APIs don't contain the string 'submit'.
Rename it to make things uniform. This is also helping while
adding a host translational layer wherein we are using
usb_submit_**_msg string to name APIs.
Signed-off-by: Vivek Gautam
---
common/usb.c |4 ++--
common/usb_k
Add wrapper functions for usb layer operations for control, bulk,
interrupt transfers to accomodate support for driver model.
Signed-off-by: Vivek Gautam
---
common/usb.c | 99
common/usb_hub.c |2 +-
include/dm/uclass-id.h |
Hi Marek, Simon,
This patch-series comes as a update for an earlier posted series[1]
"[PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support"
which was posted long back.
We had discussion to introduce the driver model instead of the approach used
in [1]. The driver model seems pr
Adding a UCLASS driver for USB based on driver-model, to facilitate
binding mutiple host-controllers to their respective drivers, and
thereby enable using mutiple controllers simultaneously on a platform.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/Kconfig |9
drivers/usb/host
Adding support for driver model and necessary callbacks
in ohci/ehci/xhci.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/ehci-hcd.c | 36
drivers/usb/host/ohci-hcd.c | 35 ---
drivers/usb/host/xhci.c | 34 +
With driver model now we can enable both EHCI and XHCI on
Exynos5250.
Signed-off-by: Vivek Gautam
---
include/configs/exynos5-common.h|3 +++
include/configs/exynos5250-common.h |3 +++
include/configs/smdk5250.h |2 ++
3 files changed, 8 insertions(+)
diff --git a/incl
Add devices for XHCI-HCD and EHCI-HCD in exynos5 family.
Signed-off-by: Vivek Gautam
---
arch/arm/dts/exynos5.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 238acb8..5cdf406 100644
--- a/arch/arm/dts/exynos5.dtsi
++
Hello,
On 02/18/2015 06:01 AM, Simon Glass wrote:
+Stephen who might have an opinion on this.
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak wrote:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull mode is not
This commit adds implementation of driver model gpio pull
setting to s5p gpio driver.
Signed-off-by: Przemyslaw Marczak
Cc: Simon Glass
Cc: Minkyu Kang
Reviewed-by: Simon Glass
---
Changes v2:
- adjust code after added gpio pull enum to gpio api
---
drivers/gpio/s5p_gpio.c | 28 +
Hello Simon,
On 02/18/2015 06:02 AM, Simon Glass wrote:
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak wrote:
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibil
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by i
The dw mmc driver init priority was always the same: ch 0, ch 1, ch 2.
On some boards (e.g. Odroid XU3) the dwmmc driver is enabled for all
mmc channels. In this case, when boot device is switchable (SD/eMMC),
the default MMC device will be 0 or 1.
Change the init priority to boot device, always in
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.
To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.
Signed-off-by: Przemyslaw Marczak
Cc: Pantelis Antoniou
Reviewed-by:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull modes are defined by proper enum and can be:
- UP
- DOWN
- NONE
- UNKNOWN
Signed-off-by: Przemyslaw Marczak
CC: Simon Glass
Reviewed-by: Simon Glass
---
Changes v2:
- add enum wit
On Wed, 18 Feb 2015 15:16:27 +0530
Akshay Saraswat wrote:
> This patch adds workaround for ARM errata 798870 which says
> "If back-to-back speculative cache line fills (fill A and fill B) are
> issued from the L1 data cache of a CPU to the L2 cache, the second
> request (fill B) is then cancelled
On Wed, 18 Feb 2015 15:16:28 +0530
Akshay Saraswat wrote:
> This patch adds workaround for the ARM errata 799270 which says
> "If the L2 cache logic clock is stopped because of L2 inactivity,
> setting or clearing the ACTLR.SMP bit might not be effective. The bit is
> modified in the ACTLR, meani
Hi Akshay,
> This patch adds code to shutdown secondary cores.
> When U-boot comes up, all secondary cores appear powered on,
> which is undesirable and causes side effects while
> initializing these cores in kernel.
>
> Secondary core power down happens in following steps:
>
> Step-1: After Exy
Hi Lukasz,
>Hi Akshay,
>
>> This patch adds code to shutdown secondary cores.
>> When U-boot comes up, all secondary cores appear powered on,
>> which is undesirable and causes side effects while
>> initializing these cores in kernel.
>>
>> Secondary core power down happens in following steps:
>>
Hello,
>On Wed, 18 Feb 2015 15:16:27 +0530
>Akshay Saraswat wrote:
>
>> This patch adds workaround for ARM errata 798870 which says
>> "If back-to-back speculative cache line fills (fill A and fill B) are
>> issued from the L1 data cache of a CPU to the L2 cache, the second
>> request (fill B) is
Hello,
On 02/18/2015 05:23 AM, Simon Glass wrote:
On 16 February 2015 at 08:13, Przemyslaw Marczak wrote:
This commit enables the following configs:
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
This increases the performance of memcpy/memset
and also reduces the boot time.
This was teste
Hello,
I have a Samsung Exynos 5420 Arndale Octa Board and I am trying to run Xen
4.5 on it.
I have successfully managed to configure and patch XEN and the kernel for
the board.
The problem is that XEN doesn't match the correct CPU mode for its boot.
-XEN early debug-
Hello,
On 02/18/2015 05:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 16 February 2015 at 08:21, Przemyslaw Marczak wrote:
Hello,
On 02/16/2015 04:13 PM, Przemyslaw Marczak wrote:
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performa
Hi Tom,
On Fri, 2015-02-13 at 09:23 +0300, Alexey Brodkin wrote:
> Dear Tom,
>
> The following changes since commit
> bd2a4888b123713adec271d6c8040ca9f609aa2f:
>
> sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART (2015-02-11
> 19:43:45 -0500)
>
> are available in the git repository at:
>
Hi Simon,
On 02/18/2015 05:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 16 February 2015 at 08:13, Przemyslaw Marczak wrote:
Signed-off-by: Przemyslaw Marczak
---
Kconfig | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/Kconfig b/Kconfig
index
Hello Simon,
On 02/18/2015 05:32 AM, Simon Glass wrote:
On 16 February 2015 at 08:13, Przemyslaw Marczak wrote:
Reduce the boot time of Odroid X2/U3 by disabling the memset
at malloc init.
This was tested on Odroid X2.
A quick test with checking gpio pin state using the oscilloscope.
Boot tim
Hello Stephen,
On 02/17/2015 11:39 PM, Stephen Warren wrote:
On 02/17/2015 02:43 PM, Stephen Warren wrote:
On 02/16/2015 08:13 AM, Przemyslaw Marczak wrote:
This patchset reduces the boot time for ARM architecture,
Exynos boards, and boards with DFU enabled.
I tested this series on NVIDIA's
Hi Tom,
The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
are available in the git repository at:
http://git.denx.de/u-boot-fdt.git
for you to fetch changes up to c71a0164d9b23e624552fb614bcb426a1
On 02/17/2015 05:47 PM, Nishanth Menon wrote:
On Tue, Feb 17, 2015 at 4:27 PM, Murali Karicheri wrote:
is complete the boot-loader sets the PC to the first MSMC address
0x0c00. The u-boot.bin is linked to the address 0x0c001000.
why not just shift u-boot.bin to start of MSMC address?
+mailing list
On 18 February 2015 at 06:14, Simon Glass wrote:
> Hi Vivek,
>
> On 18 February 2015 at 03:40, Vivek Gautam wrote:
>> Hi Marek, Simon,
>>
>> This patch-series comes as a update for an earlier posted series[1]
>> "[PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host suppo
Hi Tom,
On Wed, 2015-02-18 at 15:35 +0300, Alexey Brodkin wrote:
> Hi Tom,
>
> Could you please pull those changes?
Just realized you already pulled my the changes.
Probably I missed your reply and was too lazy to check latest changes in
U-Boot at say http://git.denx.de/?p=u-boot.git;a=shortlog
Hi Simon,
On Wed, Feb 18, 2015 at 6:45 PM, Simon Glass wrote:
> +mailing list
>
> On 18 February 2015 at 06:14, Simon Glass wrote:
>> Hi Vivek,
>>
>> On 18 February 2015 at 03:40, Vivek Gautam wrote:
>>> Hi Marek, Simon,
>>>
>>> This patch-series comes as a update for an earlier posted series[
Hi Simon,
On Thu, 2015-02-05 at 21:41 -0700, Simon Glass wrote:
> +config SYS_MALLOC_F
> + bool "Enable malloc() pool before relocation"
> + default 0x400
I'm wondering if default value here should be of type "bool" but not a
hex value?
Probably this is just a copy paste from the followi
Hi Adam,
On 02/18/2015 03:58 AM, Adam YH Lee wrote:
> The ECC scheme selection algorithm in OMAP GPMC appears to be left untested
> when
> BCH8 handling code was added. Running 'nandecc sw' defaults to HAM1 even if
> the board is using another scheme (ex. OMAP_ECC_BCH8_CODE_HW_DETECTION_SW on
> O
p.s.
On 18-02-15 10:21, Ian Campbell wrote:
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede
All 4 patches: Acked-by: Ian Campbell
Pushed to u-boot-su
Hi,
On 18-02-15 10:21, Ian Campbell wrote:
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede
All 4 patches: Acked-by: Ian Campbell
Thanks for the revie
Hello,
The documentation [1] for the AM335x defines a manual process for UART
booting as including the steps...
When '' appear select XMODEM -> Send "u-boot-spl.bin", and then...
When '' appear select YMODEM -> Send "u-boot.img"
Is there a pre-existing tool or script around that will au
On Wed, Feb 18, 2015 at 7:12 AM, Vitaly Andrianov wrote:
>
>
> On 02/17/2015 05:47 PM, Nishanth Menon wrote:
>>
>> On Tue, Feb 17, 2015 at 4:27 PM, Murali Karicheri
>> wrote:
>
> is complete the boot-loader sets the PC to the first MSMC address
> 0x0c00. The u-boot.bin is linked t
According to the i.MX6Q Reference Manual, clocks must be gated when
switching input clocks of async clock muxes. So use clock gates. Avoid
ldb_di0_ipu clock, because there is no clock gate for this signal.
There have never been any complaints about problems with the old code,
but the new approach
>Are you saying that it is completely consistent that when TFTPing from a specific TFTP
server to u-boot you always get these time-outs, but with a different one you never get them?
Exactly. Even when I try to download uImage from kvm host machine, I still got timeouts.
But should I try to downlo
On 02/17/2015 11:13 PM, Jan Kiszka wrote:
On 2015-02-17 22:03, Stephen Warren wrote:
On 02/16/2015 05:54 AM, Jan Kiszka wrote:
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this v
On 02/17/2015 10:01 PM, Simon Glass wrote:
+Stephen who might have an opinion on this.
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak wrote:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull mode is not defined
Hi,
Here's what I think happens:
When working with large TFTP packets (probably 4096 bytes, as set in
your board config file), U-Boot TFTP code sends wrong acknowledges for
the TFTP packets. If the TFTP server implementation is too strict (the
OpenBSD server is a good example), the transfer will
Hi Andreas, for OMAP3 and AM35xx boards, it would have been ok omitting the
CONFIG_BCH check and simply use CONFIG_NAND_OMAP_ECCSCHEME.
Those boards use the ecc scheme config already. However I just wasn't 100%
sure if I could rely on this config for all TI OMAP/AM based boards. I know
OMAP3
and A
Hello Rob,
Sorry for delay.
On 01/26/2015 04:44 PM, Rob Herring wrote:
Currently, an environment variable must be used to store the randomly
generated UUID for each partition. This is not necessary, so make storing
the UUID optional. Now passing uuid_disk and uuid are optional when random
UUIDs
Hello Rob,
On 01/26/2015 04:43 PM, Rob Herring wrote:
The gpt command always reports success even if writing the partition table
failed. Propagate the return value of gpt_restore so we get proper status
reported.
Signed-off-by: Rob Herring
---
common/cmd_gpt.c | 4 ++--
1 file changed, 2 in
I am trying to bring up xen suing u-boot that has this patch. Unfortunately as
soon as the code tries to call _nonsec_init through secure_ram_addr in
arm7_init_nonsec function in virt-v7.c I get an undefined instruction
exception. I suspect the CONFIG_ARMV7_SECURE_BASE needs to be defined to a
On Tue, Feb 17, 2015 at 04:47:14PM -0800, Adam Lee wrote:
> I have a Gumstix Overo (OMAP3) with a 512MiB NAND. I have been validating
> BCH8 ecc scheme and one of the problems I ran into is this:
>
> arm-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will not fit in
> region `.sram'
> arm-linu
On Tue, Feb 17, 2015 at 08:22:17PM -0700, Simon Glass wrote:
> +tom, and pruning the cc list a little
>
> Hi,
>
> On 26 January 2015 at 18:27, Simon Glass wrote:
> > This series adds debug UART infrastructure which can in principle be used on
> > any architecture. It works best with those that
Had a conversation with Ash @ Gumstix and he pointed out relying on
CONFIG_NAND_OMAP_ECCSCHEME could be dangerous as it could be anything other
than the two SW ECC schemes available for OMAP3.
Also it looks like making a selection between OMAP_ECC_BCH8_CODE_HW and
OMAP_ECC_BCH8_CODE_HW_DETECTION_S
This patch adds functionality to getvar command to get the userdata partition
size.
Signed-off-by: Dileep Katta
---
common/fb_mmc.c | 38 ++
drivers/usb/gadget/f_fastboot.c | 2 ++
include/fb_mmc.h| 2 ++
3 files changed, 42 i
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw
where 'hamming' is still
From: Stephen Warren
This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren
---
v2:
* Use clrbits_le32() rather than open-code read/modify/write statements.
* Update pinmux_set_tristate_input_clamping to match.
---
arch/arm/cpu/tegra-common/pinmux-com
From: Stephen Warren
Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
The new spreadsheet sets T
This series is a collection of changes in core DM, sandbox, x86 and PCI code
to implement a PCI uclass and associated operations. Some basic tests are
provided as well.
As is becoming common with DM conversions, the existing structure (here
struct pci_controller) becomes per-bus uclass data. This
This strdup() is missing a check. Add it.
Signed-off-by: Simon Glass
---
drivers/i2c/i2c-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index a6991bf..b890806 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
These are missing a size value. Add one in each case.
Signed-off-by: Simon Glass
---
arch/sandbox/dts/sandbox.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 9ce31bf..1ccfdee 100644
--- a/arch/sandbox/
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass
---
drivers/pci/Makefile | 2 +-
drivers/pci/pci.c| 281 +
drivers
This function is missing a prototype but is more widey useful. Add it.
Signed-off-by: Simon Glass
---
include/fdtdec.h | 11 +++
lib/fdtdec.c | 2 +-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1bc70db..2a96a0a 100644
---
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.
TODO: Add more header file comments to the new parts of
Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/pci.c | 63 ++---
arch/x86/dts/chromebook_link.dts| 7 +
board/google/chromebook_link/link.c | 9 ++
configs/coreboot-x86_defconfig |
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).
Update the error return value to allow these different situations to be
distinguished.
Signed-off-
Both of these values are useful for understanding what is going on, so show
them both.
The requested number comes from a device tree alias. The allocated one is
set up when the device is activated, and is unique throughout the uclass.
Signed-off-by: Simon Glass
---
test/dm/cmd_dm.c | 4 ++--
1
This function does not unmap what it maps. Correct it.
Signed-off-by: Simon Glass
---
common/cmd_mem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bcb3ee3..855aa57 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -1
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.
Signed-off-by: Simon Glass
---
drivers/pci/Makefile | 1 +
drivers/pci/pci-emul-uclass.c
Add some basic tests to check that things work as expected with sandbox.
Signed-off-by: Simon Glass
---
test/dm/Makefile | 1 +
test/dm/pci.c| 59
test/dm/test.dts | 17
3 files changed, 77 insertions(+)
create mode
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass
---
common/cmd_sf.c| 2 +-
common/cros_ec.c | 2 +-
Enable PCI options so that sandbox can be used for testing this bus with
driver model.
Signed-off-by: Simon Glass
---
configs/sandbox_defconfig | 3 +++
include/configs/sandbox.h | 4
2 files changed, 7 insertions(+)
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index
Add a driver which can access emulations of devices and make them available
in sandbox.
Signed-off-by: Simon Glass
---
drivers/pci/Kconfig | 10 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_sandbox.c | 79 +++
3 files changed, 90 ins
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass
Add the required header information, device tree nodes and I/O accessor
functions to support PCI on sandbox. All devices are emulated by drivers
which can be added as required for testing or development.
Signed-off-by: Simon Glass
---
arch/sandbox/Kconfig | 7 ++
arch/san
At present the device is not active when the probe() method is called. But
some probe() methods want to set up the device and this can involve
accessing it through normal methods. For example a PCI bus may wish to
set up its PCI parameters using calls to pci_hose_write_config_dword() and
similar.
Move chromebook_link over to driver model for PCI.
This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)
This does not really
At present we do more in this function than we should. Create a new
x86_post_cpu_init() which can be called from the board file when needed
(e.g. in board_early_init_f(). This allows us to use driver model for
our x86_post_cpu_init() function.
It is likely that some future refactoring will improve
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.
Signed-off-by: Simon Glass
---
arch/x86/cpu/pci.c | 40
arch/x86/include/asm/pci.h | 8
arch/x86/lib/Makefile | 2 ++
drivers/pci/Makefile
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