Hello,
>On Wed, 18 Feb 2015 15:16:27 +0530
>Akshay Saraswat <aksha...@samsung.com> wrote:
>
>> This patch adds workaround for ARM errata 798870 which says
>> "If back-to-back speculative cache line fills (fill A and fill B) are
>> issued from the L1 data cache of a CPU to the L2 cache, the second
>> request (fill B) is then cancelled, and the second request would have
>> detected a hazard against a recent write or eviction (write B) to the
>> same cache line as fill B then the L2 logic might deadlock."
>>
>> Signed-off-by: Kimoon Kim <kimoon....@samsung.com>
>> Signed-off-by: Akshay Saraswat <aksha...@samsung.com>
>> Reviewed-by: Simon Glass <s...@chromium.org>
>> Tested-by: Simon Glass <s...@chromium.org>
>> ---
>> Changes since v2:
>> - No change.
>>
>> Changes since v1:
>> - Added Reviewed-by & Tested-by.
>> - Added space before */ on line # 40.
>>
>> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> index e36f2fa..7335a1e 100644
>> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>> @@ -46,6 +46,28 @@ enum {
>>
>> #ifdef CONFIG_EXYNOS5420
>> /*
>> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
>> + * stalled for 1024 cycles to verify that its hazard condition still exists.
>> + */
>
>Having the ARM errata number mentioned in the comment here would make
>the purpose of this code much more clear to anyone looking at it later
>in the future.
>
>Also isn't this a general purpose Cortex-A15 r2pX workaround,
>also potentially useful for the other non-Exynos SoCs too?
Yes, you are right.
I'll mention errata number and will move it to armv7/cpu.c.
>
>> +void set_l2cache(void)
>> +{
>> + uint32_t val;
>> +
>> + /* Read MIDR for Primary Part Number */
>> + mrc_midr(val);
>> + val = (val >> 4);
>> + val &= 0xf;
>> +
>> + /* L2ACTLR[7]: Enable hazard detect timeout for A15 */
>> + if (val == 0xf) {
>> + mrc_l2_aux_ctlr(val);
>> + val |= (1 << 7);
>> + mcr_l2_aux_ctlr(val);
>> + mrc_l2_ctlr(val);
>> + }
>> +}
>> +
>> +/*
>> * Pointer to this function is stored in iRam which is used
>> * for jump and power down of a specific core.
>> */
>
>
>
>--
>Best regards,
>Siarhei Siamashka
Regards,
Akshay Saraswat
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
