The "cp" command has not worked since
commit 0628ab8ec59834f98ede267edd21ddb8ba0bb57b,
because of the following lines, which set the destination
and the source to the same address.
buf = map_sysmem(addr, bytes);
src = map_sysmem(addr, bytes);
Signed-off-by: Masahiro Yamada
---
c
Dear man:
I'm sorry to troubling you,but i come cross some problem that can't
be solved.I want to use U-Boot as a bootloader to bulid the embeded linux
development platform.I'm using TI's LM3S8962 processor ,but i can't find
the type or similar in board/ti directory.So I can't complement th
Dear Rajeshwari Shinde,
On 03/04/13 20:54, Rajeshwari Shinde wrote:
> This patch enables GPIO Command for EXYNOS5.
> Function has been added to asm/gpio.h to decode the
> input gpio name to gpio number.
> example: gpio set gpa00
>
> Signed-off-by: Rajeshwari Shinde
> ---
> Changes in V2:
>
Dear Piotr Wilczek,
On 17/05/13 21:55, Piotr Wilczek wrote:
> This patchset add support for a new Samsung board Trats2.
> The board use now new i2c framework.
> Support for new multi function pmic max77693 is added.
>
> This patchset depends on:
> commit: 8faefadb7305b95d02df38bd2ea61429d5948
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains:
starting with OMAP3630. There are three modes of operation:
* Bypass - the default, it just follows the vdd
Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.
Signed-off-by: Andrii Tseglytskyi
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |9 +
arch/arm/cpu/armv7/omap5/prcm-regs.c
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:
* Bypass - the default, it just follows the vdd v
Dear Minkyu Kang,
> -Original Message-
> From: Minkyu Kang [mailto:mk7.k...@samsung.com]
> Sent: Tuesday, May 21, 2013 10:36 AM
> To: Piotr Wilczek
> Cc: u-boot@lists.denx.de; Kyungmin Park; Lukasz Majewski
> Subject: Re: [PATCH v3 0/12] Introduce Samsung's new board Trats2
>
> Dear Piotr
CAP register don't have any information for 8-bit buswidth support
on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.
Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
mmc_set_bus_width even if controller doesn't support.
Below change has code information.
This patch adds watchdog support for Vybrid MVF600 platform.
Signed-off-by: Alison Wang
---
Changes in v3: None
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchd
This patch adds the IOMUX support for Vybrid MVF600 platform.
There is a little difference for IOMUXC module between MVF600 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
MVF600, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Alison Wang
---
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this
This series contain the support for Freescale Vybrid MVF600 CPU and MVF600TWR
board.
Vybird devices are built on an asymmetrical-multiprocessing architecture
using ARM cores. The families in the Vybrid portfolio span entry-level,
single core Cortex-A class SoCs all the way to dual heterogeneous c
This patch adds FEC support for Vybrid MVF600 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for MVF600 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_R
Dear Bo Shen,
Bo Shen writes:
>Add Atmel sama5d3 SoC new pmc register
>
>Signed-off-by: Bo Shen
>
>---
>Changes in v3:
> - New splitted patch file.
>
>Changes in v2:
> - No change
>
> arch/arm/include/asm/arch-at91/at91_pmc.h | 23 +++
> 1 file changed, 23 insertions(+)
a
Dear Bo Shen,
Bo Shen writes:
>Add OHCI support for sama5d3x devices
>
>Signed-off-by: Bo Shen
>
>---
>Changes in v3:
> - Rebase to u-boot-atmel master branch
>
>Changes in v2:
> - No Change
>
> drivers/usb/host/ohci-at91.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(
Dear Bo Shen,
Bo Shen writes:
>Add sama5d3xek support with following feature
> - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
> - boot from SPI flash support
> - boot from SD card support
> - LCD support
> - EMAC support
> - USB OHCI support
>
>Signed-off-by: Bo Shen
>
Dear Bo Shen,
Bo Shen writes:
>This patch implement following things
> - The link no longer accessable
> - Remove the error configuration command
> - Update soldered data flash memory map
> - Update at91sam9m10g45ek memory size to 128MiB
>
>Signed-off-by: Bo Shen
>
>---
>doc/README.at91 |
Dear Bo Shen,
Bo Shen writes:
>Add NAND partition table, EK board support boot up NAND flash using
>the same NAND partition table
>
>Add Index in this file
>
>Signed-off-by: Bo Shen
>
>---
>doc/README.at91 | 21 -
> 1 file changed, 20 insertions(+), 1 deletion(-)
applied to
Dear Bo Shen,
Bo Shen writes:
>This patch add following EK information
> - at91sam9n12ek, at91sam9x5ek
> - sama5d3xek
>
>Signed-off-by: Bo Shen
>
>---
>doc/README.at91 | 42 ++
> 1 file changed, 42 insertions(+)
applied to u-boot-atmel/master, thanks!
Dear Albert Aribaud,
please pull the following changes from u-boot-atmel/master into
u-boot-arm/master.
The following changes since commit d0a51373131c4ba565a2391d5ed78b87c406ce98:
at91sam9260ek: move board id setup to config header (2013-05-12 16:49:14
+0200)
are available in the git reposi
MVF600TWR is a board based on Vybrid MVF600 SoC.
This patch adds basic support for Vybrid MVF600TWR board.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: TsiChung Liew
---
Changes in v3:
- Replace BOOT_FROM by BOOT_OFFSET
- Enable CONFIG_OF_LIBFDT option
- Add useful define
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
It aligns Vybrid MVF600 platform with i.MX platform. As there are
some differences between MVF600 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/mvf600 directory.
Signed-off-by: Alison Wang
---
Changes
Dear Sergey Yanovich,
> PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
> default run mode. Activating the mode early significantly speeds
> up boot process.
>
> Signed-off-by: Sergey Yanovich
What's the difference? Where does this macro get used ?
> ---
> arch/arm/cpu/pxa/px
Dear Sergey Yanovich,
> 2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
> "The PXA27x processor cache configuration is identical to that of
> the PXA255 processor."
>
> As a result, it is perfectly legitimate to use PXA25X
> 'lock_cache_for_stack' on PXA27X as well.
>
> Signed
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:39 +0200, Marek Vasut wrote:
> > 2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
> > "The PXA27x processor cache configuration is identical to that of
> > the PXA255 processor."
> >
> > As a result, it is perfectly legitimate to use PX
Dear Sergey Yanovich,
> LP-8x4x is a programmable automation controller by ICP DAS. It is
> shipped with outdated U-Boot v1.3.0
>
> This patch adds enough supports to boot the board:
> - 128M of 128M SDRAM
> - 32M of 48M NOR Flash memory
> - 1 of 4 Serial consoles (PXA FFUART)
> - 2 of 2 Ethe
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:35 +0200, Marek Vasut wrote:
> > PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
> > default run mode. Activating the mode early significantly speeds
> > up boot process.
> What's the difference? Where does this macro get used ?
Differe
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 12:39 +0200, Marek Vasut wrote:
> > > 2.2.5.2 of Marvell PXA27x Processor Family Developers Manual says:
> > > "The PXA27x processor cache configuration is identical to that of
> > > the PXA255 processor."
> > >
> > > As a resul
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 12:35 +0200, Marek Vasut wrote:
> > > PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
> > > default run mode. Activating the mode early significantly speeds
> > > up boot process.
> >
> > What's the difference?
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:55 +0200, Marek Vasut wrote:
> > Difference -- approx. 2.5 times faster system.
> >
> > Who uses it -- ex. LP-8x4x board, support for which I am trying to merge
> > in a separate patch. Any PXA27X board can use it.
>
> Why don't you enable it globally t
Dear Akshay Saraswat,
On 22/03/13 21:26, Akshay Saraswat wrote:
> According to the latest exynos5 user manual, the equation for
> calculating PLL output was changed to
> FOUT= MDIV x FIN/(PDIV x 2^SDIV)
> earlier it was
> FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
> So updating the clock code according
On 12/15/2012 07:04 PM, Joe Hershberger wrote:
>> -#ifndef CONFIG_BOOTCOMMAND
>> -#define CONFIG_BOOTCOMMAND
>>\
>> - "bootp; "
>>\
>> - "setenv bootargs root=/dev/nf
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 12:55 +0200, Marek Vasut wrote:
> > > Difference -- approx. 2.5 times faster system.
> > >
> > > Who uses it -- ex. LP-8x4x board, support for which I am trying to
> > > merge in a separate patch. Any PXA27X board can use it.
>
[..]
> Actually, I wonder if Linux's cpufreq still does depend on bootloader speed
> settings. Especially the turbo bit. Can you please check that? It'd be
> interesting to know ...
>
> I'd say enable it by default ... I probably have all the PXA devices
> supported in U-Boot and I'm quite sure n
Dear Marek Vasut,
On Tue, 2013-05-21 at 12:54 +0200, Marek Vasut wrote:
> SRAM is just the in-CPU bit of fast RAM. What do you mean by "battery-backup"
> ?
Yes, you are right. It is 'for high speed code or data storage preserved
during low-power states' using a quote from PXA270 EMTS (top of pag
On 22/03/13 15:33, Akshay Saraswat wrote:
> This patch enables the uart tx/rx fifo. Now that fifo is enabled,
> the uart read/write functions are modfied to check the UFSTAT register
> for fifo status instead of UTRSTAT (as required with fifo's enabled).
> Tested by booting linux kernel. Before ena
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 12:54 +0200, Marek Vasut wrote:
> > SRAM is just the in-CPU bit of fast RAM. What do you mean by
> > "battery-backup" ?
>
> Yes, you are right. It is 'for high speed code or data storage preserved
> during low-power states' usin
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.
Signed-off-by: Sergey Yanovich
---
Changes for v2:
- activate turbo mode and fast bus by default
---
arch/arm/cpu/pxa/pxa2xx.c |7 ++-
1
Dear Marek Vasut,
On Tue, 2013-05-21 at 13:38 +0200, Marek Vasut wrote:
> Yes, it's just an in-CPU RAM.
Well, it is not 'just' RAM. It preserves its state during deep sleep and
power off modes.
> > Anyway, SRAM preserves its state when power is off. Poweroff time could
> > be in years with a bac
Dear Henrik Nordström,
In message <1368792981.765.21.camel@localhost> you wrote:
>
> > There is a common, architecture-independent C API that implements
> > cache flushing/invalidation; please re-read the summary at [1]
>
> Sorry I missed that discussion. Had a bit too much mail for a while.
No
Dear Scott A,
In message you wrote:
>
> Hi,I am attempting to read a set of files from the fat file system into a
> location in memory.This is easy using the command interface using somethin
> g likefatload mmc 0:1 0x4800 file.txt
> However i want to do this in a standalone program. Is there
Dear Rajeshwari Shinde,
On 12/05/13 00:04, Simon Glass wrote:
> From: Rajeshwari Shinde
>
> Support interfaces with a preamble before each received message.
>
> We handle this when the client has requested a SPI_XFER_END, meaning
> that we must close of the transaction. In this case we read unt
Dear Henrik,
In message <1368920138.23379.14.camel@localhost> you wrote:
>
> I think it would be a great addition to add generic filesystem
> operations to the standalone API. The fs_read() and fs_write() functions
> should be possible to export via the standalone API as-is, but should
> probably
Dear Kuo-Jung Su,
In message
you wrote:
>
> How about making the weak aliased arch_preboot_os() global, and then
> get it invoked
> in both bootm & go?
> It looks much pretty to me, and we don't even worry about the i-cache issues.
That would not really help as it would be architecure specific,
Dear Marek Vasut,
In message <1369070715-9585-2-git-send-email-ma...@denx.de> you wrote:
> Prefix HOSTCC and CC with CCACHE variable to allow easy use of ccache.
> In case the user wants to use ccache, exporting CCACHE=ccache will do
> the trick. It is of course possible to either make the cross-c
Dear Marek Vasut,
In message <1369070715-9585-3-git-send-email-ma...@denx.de> you wrote:
> + # Use per-board CCACHE directory
> + if [ "x${CCACHE}" != "x" ] ; then
Why not simply:
if [ "${CCACHE}" ] ; then
?
> + export CCACHE_DIR="`${CCACHE} -s | grep "^cache direc
Dear Michael Heimpold,
In message <1369078482-5863-1-git-send-email-m...@heimpold.de> you wrote:
> Closing a file descriptor does not guarantee that the data has been
> successfully saved to disk, as the kernel might defer the write.
What is the exact problem you are trying to fix?
I mean, when
Hello,
On Thu, May 16, 2013 at 5:37 PM, Henrik Nordström
wrote:
> Or maybe just punt it. If you are on an arch with incoherent caches then
> make sure to make use of the cache command to flush caches and maybe
> even disable caches before using go.
This is indeed the behaviour one would expect fr
On 26/03/13 18:37, Inderpal Singh wrote:
> The Arndale board is based on samsung's exynos5250 SOC.
>
> First patch just removes the redundant SPI configs from common exynos5250
> config file. Second patch moves the board specific configs to board specific
> config file. The third adds the andale b
Hi All,
I use the DWMMC driver in u-boot mainline on exynos board and face the
following issue.
I do a mmc rescan 3 times, then fourth time I get a DATA ERROR, which
is due to FIFO underun/overun, after which I don't even get Command
done interrupt.
Later on the mmcinfo value also is displayed wr
This patch add new functions to pmic max77686 to set voltage and mode.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Minkyu Kang
CC: Rajeshwari Shinde
Acked-by: Rajeshwari Shinde
---
Changes in v2:
- changed printf to debug
drivers/power/pmic/pmic_max77686.c | 186
This patch add support for new multi function pmic max77693.
The driver is split into three modules: pmic, muic and fuelgage.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Minkyu Kang
---
Makefile |1 +
drivers/power/mfd/Makefile| 49 +
Hi,
I think this reviewed already, but have a very few comments.
On Wed, Jan 23, 2013 at 12:00 PM, Rajeshwari Shinde
wrote:
> This patch adds driver for the gigabyte devices
> GD25LQ and GD25Q64B required for Snow Board.
>
> Signed-off-by: Rajeshwari Shinde
> ---
> Changes in V2:
> - Ad
Hi Benoît,
On Mon, May 20, 2013 at 12:39 PM, Benoît Thébaudeau
wrote:
> Can you test this series on mx31pdk (directly changed by this series), and
> some
> other i.MX EVK (e.g. ARMv7, so mx51evk or mx53*) board please? That should be
> enough for ARM.
I don't have access to my mx31pdk currentl
This patch fix wrong value returned by 's5p_gpio_part_max' function
for Exynos4412.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Minkyu Kang
---
arch/arm/include/asm/arch-exynos/gpio.h | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arc
On 05/21/2013 06:02 AM, Alison Wang wrote:
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&ccm->ccgr6);
+ if (enable)
+ reg |= CCM_CCGR6_OCOTP_CTRL_
Hi,
On Tue, May 21, 2013 at 6:24 PM, Rajeshwari Birje
wrote:
> Hi All,
>
> I use the DWMMC driver in u-boot mainline on exynos board and face the
> following issue.
>
> I do a mmc rescan 3 times, then fourth time I get a DATA ERROR, which
> is due to FIFO underun/overun, after which I don't even
Dear Wolfgang Denk,
> Dear Marek Vasut,
>
> In message <1369070715-9585-2-git-send-email-ma...@denx.de> you wrote:
> > Prefix HOSTCC and CC with CCACHE variable to allow easy use of ccache.
> > In case the user wants to use ccache, exporting CCACHE=ccache will do
> > the trick. It is of course po
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 13:38 +0200, Marek Vasut wrote:
> > Yes, it's just an in-CPU RAM.
>
> Well, it is not 'just' RAM. It preserves its state during deep sleep and
> power off modes.
So does RAM during sleep state ;-)
> > > Anyway, SRAM preserves
Dear Wolfgang Denk,
> Dear Marek Vasut,
>
> In message <1369070715-9585-3-git-send-email-ma...@denx.de> you wrote:
> > + # Use per-board CCACHE directory
> > + if [ "x${CCACHE}" != "x" ] ; then
>
> Why not simply:
>
> if [ "${CCACHE}" ] ; then
>
> ?
>
> > + export CCACHE_D
On Tue, 2013-05-21 at 13:22 +0200, Marek Vasut wrote:
> > Actually, I wonder if Linux's cpufreq still does depend on bootloader speed
> > settings. Especially the turbo bit. Can you please check that? It'd be
> > interesting to know ...
> >
> > I'd say enable it by default ... I probably have all
On Tue, 2013-05-21 at 17:00 +0200, Marek Vasut wrote:
> > Yes, the patch as it is will only affects relocation speed and preserve
> > SRAM from corruption.
>
> Now this is the right (convincing) argument! What kind of corruption ? When
> does
> it occur ?
The whole 256 kB of SRAM could be used
Hi Alison,
On Tuesday, May 21, 2013 11:02:55 AM, Alison Wang wrote:
> This series contain the support for Freescale Vybrid MVF600 CPU and MVF600TWR
> board.
>
> Vybird devices are built on an asymmetrical-multiprocessing architecture
> using ARM cores. The families in the Vybrid portfolio span en
Hi Kees,
On Tue, 21 May 2013 14:38:01 +0200, Kees Jongenburger
wrote:
> To my
> understanding also enabling d-cache on ARM has no effect as long as
> the MMU is not turned on so I totally miss the point.
Enabling dcache gives DDR access performance benefits regardless of
enabling MMU.
> Greeti
Hi Alison,
On Tuesday, May 21, 2013 11:02:56 AM, Alison Wang wrote:
> This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
>
> It aligns Vybrid MVF600 platform with i.MX platform. As there are
> some differences between MVF600 and i.MX platforms, the specific
> codes are in the
Hi,
I have a simple question like these parts are legacy flashes i guess.
Could you please tell me on which boards these were used?
Thanks,
Jagan.
On Fri, Apr 26, 2013 at 1:32 PM, Kuo-Jung Su wrote:
> From: Kuo-Jung Su
>
> Signed-off-by: Kuo-Jung Su
> ---
> drivers/mtd/spi/winbond.c | 17 +
Hi Alison,
On Tuesday, May 21, 2013 11:02:57 AM, Alison Wang wrote:
> This patch adds the IOMUX support for Vybrid MVF600 platform.
>
> There is a little difference for IOMUXC module between MVF600 and i.MX
> platform, the muxmode and pad configuration share one 32bit register on
> MVF600, but th
Hi Alison,
On Tuesday, May 21, 2013 11:02:58 AM, Alison Wang wrote:
> This patch adds FEC support for Vybrid MVF600 platform.
>
> In function fec_open(), RCR register is only set as RGMII mode. But RCR
> register should be set as RMII mode for MVF600 platform.
> This configuration is already done
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/wandboard/wand
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx53
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx6q
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx53
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx53
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx6q
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx6q
Hi Wolfgang Denx,
> > Closing a file descriptor does not guarantee that the data has been
> > successfully saved to disk, as the kernel might defer the write.
>
> What is the exact problem you are trying to fix?
>
> I mean, when exactly does adding the sync play a role?
I'm using fw_setenv duri
Hi Alison,
On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
>
> This patch adds basic support for Vybrid MVF600TWR board.
>
> Signed-off-by: Alison Wang
> Signed-off-by: Jason Jin
> Signed-off-by: TsiChung Liew
[...]
> diff --git a/
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx53
When the SDHC port number index is invalid we should return an error code
immediately.
Currently we return 'status', which has a value of zero, causing
board_mmc_init() to incorrectly return sucess.
Fix this by returning -EINVAL instead.
Signed-off-by: Fabio Estevam
---
board/freescale/mx51
Albert (& Axel),
> -Original Message-
> From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
> Sent: Saturday, May 18, 2013 11:58 AM
> To: Tom Warren
> Cc: Stephen Warren; Axel Lin; Wolfgang Denk; Heiko Schocher; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] ARM: arm720t: Add
Hello Ilya,
On 05/19/2013 12:09 PM, Ilya Bakulin wrote:
Hi list,
I use U-Boot for starting FreeBSD/arm on Globalscale DreamPlug.
On this platform FreeBSD uses "ubldr" second-stage bootloader, which is
an U-Boot API consumer and uses U-Boot API to access block devices, network,
etc.
Dreamplug ha
On Tue, May 21, 2013 at 2:32 PM, Fabio Estevam
wrote:
> When the SDHC port number index is invalid we should return an error code
> immediately.
>
> Currently we return 'status', which has a value of zero, causing
> board_mmc_init() to incorrectly return sucess.
>
> Fix this by returning -EINVAL i
On Tue, May 21, 2013 at 3:26 PM, Otavio Salvador
wrote:
> When I looked at this code I didn't change it because it raises a warning.
> So it returns the status if any failed.
Which warning are you talking about? Build warning or run-time warning?
I did not see any of these here.
status is zero
On Tue, May 21, 2013 at 3:39 PM, Fabio Estevam wrote:
> On Tue, May 21, 2013 at 3:26 PM, Otavio Salvador
> wrote:
>
> > When I looked at this code I didn't change it because it raises a
> warning.
> > So it returns the status if any failed.
>
> Which warning are you talking about? Build warning
On Tue, May 21, 2013 at 3:44 PM, Otavio Salvador
wrote:
> In the loop; it does:
>
> status |= fsl...
>
> so it gets the output of it. In case any fails it won't be 0.
It's good practice to return immediately when an error condition happens.
___
U-Boot
On Tue, May 21, 2013 at 3:49 PM, Fabio Estevam wrote:
> On Tue, May 21, 2013 at 3:44 PM, Otavio Salvador
> wrote:
>
> > In the loop; it does:
> >
> > status |= fsl...
> >
> > so it gets the output of it. In case any fails it won't be 0.
>
> It's good practice to return immediately when an error
Dear Sergey Yanovich,
> On Tue, 2013-05-21 at 17:00 +0200, Marek Vasut wrote:
> > > Yes, the patch as it is will only affects relocation speed and preserve
> > > SRAM from corruption.
> >
> > Now this is the right (convincing) argument! What kind of corruption ?
> > When does it occur ?
>
> The
Hi Alison,
On Tuesday, May 21, 2013 11:02:56 AM, Alison Wang wrote:
[...]
> diff --git a/arch/arm/include/asm/arch-mvf600/mvf_pins.h
> b/arch/arm/include/asm/arch-mvf600/mvf_pins.h
> new file mode 100644
> index 000..0fd89af
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mvf600/mvf_pins.h
On 05/20/2013 09:43:53 PM, Zhang Ying-B40530 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, May 21, 2013 2:56 AM
To: Zhang Ying-B40530
Cc: Wood Scott-B07421; u-boot@lists.denx.de; aflem...@gmail.com; Xie
Xiaobo-R63061; Tom Rini
Subject: Re: [PATCH] common/Makefile: A
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:02 +0200, Marek Vasut wrote:
> > The whole 256 kB of SRAM could be used for persistent storage with the
> > patch. Without it, part of SRAM should be dedicated for U-Boot stack or
> > be overwritten on boot.
>
> This won't hold on any PXA that uses SPL,
Dear Sergey Yanovich,
> Dear Marek Vasut,
>
> On Tue, 2013-05-21 at 21:02 +0200, Marek Vasut wrote:
> > > The whole 256 kB of SRAM could be used for persistent storage with the
> > > patch. Without it, part of SRAM should be dedicated for U-Boot stack or
> > > be overwritten on boot.
> >
> > Thi
Hi Alison,
On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
>
> This patch adds basic support for Vybrid MVF600TWR board.
>
> Signed-off-by: Alison Wang
> Signed-off-by: Jason Jin
> Signed-off-by: TsiChung Liew
[...]
> diff --git a/
Dear Sergey Yanovich,
> On Tue, 2013-05-21 at 13:22 +0200, Marek Vasut wrote:
> > > Actually, I wonder if Linux's cpufreq still does depend on bootloader
> > > speed settings. Especially the turbo bit. Can you please check that?
> > > It'd be interesting to know ...
> > >
> > > I'd say enable it
On 05/20/2013 01:07:24 AM, ying.zh...@freescale.com wrote:
From: Ying Zhang
There will clear the BSS in the function clear_bss(), the reset
address of
the BSS started from the __bss_start, and increased by four-byte
increments,
finally stoped depending on the address is equal to the _bss_en
Please change the title and the rest of the changelog to describe what
functionality you're adding and why.
On 05/20/2013 01:07:27 AM, ying.zh...@freescale.com wrote:
diff --git a/common/env_common.c b/common/env_common.c
index 906b41f..8cb81e9 100644
--- a/common/env_common.c
+++ b/common/env
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:24 +0200, Marek Vasut wrote:
> I'd love to have a uniform way to do this cache thing, really ...
Requoting the spec 'The PXA27x processor cache configuration is
identical to that of the PXA255 processor'. It looks safe to configure
all PXA2XX chipsets th
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:25 +0200, wrote:
> So why not just make this patch into
>
> -(2)
> +(0xb)
>
> instead of adding new (and undocumented ...) macro?
Point taken. Looks like I am too careful in this case.
___
U-Boot mailing li
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.
Signed-off-by: Sergey Yanovich
---
Changes for v3:
- make the change unconditional
Changes for v2:
- activate turbo mode and fast bus by def
Dear Sergey Yanovich,
> PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
> default run mode. Activating the mode early significantly speeds
> up boot process.
>
> Signed-off-by: Sergey Yanovich
OK, applied. Thanks
Best regards,
Marek Vasut
__
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