res1[] size is wrong.
It didn't consider the s5p_gpio_bank size.
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
---
arch/arm/include/asm/arch-exynos/gpio.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/
Hi Rajeshwari,
I just considered the EVT1 board.
I will resend the patch for this.
Best Regards,
Jaehoon Chung
On 06/20/2012 02:55 PM, Rajeshwari Birje wrote:
> Hi Jaehoon Chung,
>
> Had few comments...
>
> Is this changes for EVT1 board?
> As per the EVT1 Manual I have it is:
> MMC0: Correct
Sorry Luka (and all), been tied up pretty heavily recently, had to
adjust to find some free time again.
I will test your patch today and post results tonight.
2012/6/7 Luka Perkov
>
> Hi Albert,
>
> On Tue, May 15, 2012 at 09:42:59PM +0200, Albert ARIBAUD wrote:
> > >On Sun, Apr 29, 2012 at 10:1
Dear Rajeshwari Birje,
On 19 June 2012 19:57, Rajeshwari Birje wrote:
> Hi Joonyoung Shim,
>
> On Tue, Jun 19, 2012 at 1:20 PM, Joonyoung Shim wrote:
>> Hi,
>>
>> I add some comments at the below.
>>
> -- ok
>> And current SMDK5250 uses Exynos5250 EVT0 base codes,
>> but i know the kernel suppor
Hi Minkyu Kang,
This being I2C driver code should not have any dependency on EVT0 or EVT1.
Regards,
Rajeshwari Shinde.
On Wed, Jun 20, 2012 at 2:01 PM, Minkyu Kang wrote:
> Dear Rajeshwari Birje,
>
> On 19 June 2012 19:57, Rajeshwari Birje wrote:
>> Hi Joonyoung Shim,
>>
>> On Tue, Jun 19, 201
On 20/06/2012 00:54, Tom Rini wrote:
> Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
> different than "> " which is vision2. I have Cc'd the maintainer here
> as I strongly suspect this is a bug rather than intentional behavior.
>
> Cc: Stefano Babic
> Signed-off-by: Tom Ri
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to p
Hi Prabhakar,
On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar wrote:
> Hi Christian,
>
> On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote:
>> Hi,
>> Sorry for the delay, had a lot of other work to do :-/
>>
>> On Thursday, June 7, 2012, Prabhakar Lad wrote:
>>
>>
>> From: Lad, Prabh
2012/6/20 Rajeshwari Birje :
> Hi Minkyu Kang,
>
> This being I2C driver code should not have any dependency on EVT0 or EVT1.
I mean *all* arch and driver codes for Exynos5250 should support EVT1 only.
Thanks.
>
> Regards,
> Rajeshwari Shinde.
>
> On Wed, Jun 20, 2012 at 2:01 PM, Minkyu Kang wr
Hi Christian,
On Wed, Jun 20, 2012 at 14:50:41, Christian Riesch wrote:
> Hi Prabhakar,
>
> On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar wrote:
> > Hi Christian,
> >
> > On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote:
> >> Hi,
> >> Sorry for the delay, had a lot of other work to do
This patch set adds support for Exynos5250 Rev 1.0.
Exynos5250 Rev 1.0 supports DDR3 Memory configuration and
support for LPDDR2 is removed.
Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is
not yet gone into Mainline. After DWMMC driver is added to Mainline
support for generic S
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-o
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
arch/arm/include/asm/arch-exynos/clock.h | 36 +
1 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari S
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5250/clock_init.c | 714 --
board/samsung/smdk5250/clock_init.h | 149
board/samsung/smdk5250/setup.h | 718 ++
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
arch/arm/cpu/armv7/exynos/clock.c| 12 +++-
arch/arm/include/asm/arch-exynos/clock.
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/a
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c| 199 ++
board/sam
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/bo
This patch set adds support for Exynos5250 Rev 1.0.
Exynos5250 Rev 1.0 supports DDR3 Memory configuration and
support for LPDDR2 is removed.
Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is
not yet gone into Mainline. After DWMMC driver is added to Mainline
support for generic S
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-o
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari S
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/include/asm/arch-exynos/clock.h | 36 +
1 files changed, 26 insertions(+), 10 deletions(-)
diff
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
board/samsung/smdk5250/clock_init.c | 714 --
board/samsung/smdk5250/clock_init.h | 149
board/samsung/smdk5250/setu
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c|
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/cpu/armv7/exynos/clock.c| 12 +++-
arch/arm/
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/exy
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/sam
Hi Rajeshwari,
On 06/20/2012 08:11 PM, Rajeshwari Shinde wrote:
> This patch modifies the pinmux settings of MMC and UART as per
> Exynos5250 Rev 1.0
>
> Signed-off-by: Rajeshwari Shinde
> ---
> Chnages in V2:
> - None
> arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
> 1 f
Hi Jaehoon Chung
On Wed, Jun 20, 2012 at 5:28 PM, Jaehoon Chung wrote:
> Hi Rajeshwari,
>
> On 06/20/2012 08:11 PM, Rajeshwari Shinde wrote:
>
>> This patch modifies the pinmux settings of MMC and UART as per
>> Exynos5250 Rev 1.0
>>
>> Signed-off-by: Rajeshwari Shinde
>> ---
>> Chnages in V2:
>
On 06/19/2012 01:50 PM, Wolfgang Denk wrote:
> Dear Tom Rini,
>
> In message <1335480396-29478-1-git-send-email-tr...@ti.com> you wrote:
>> We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
>> in which mkconfig places after in
>> the generated config file. This is used when a
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms
(where our cacheline size is 64 not 32). First, the dcache_off call
that ehci-omap had been doing was now not happening soon enough to paper
over the
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut
Signed-off-by: Tom Rini
---
drivers/usb/host/ehci-omap.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host/ehci-omap.c b
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Sricharan R
Signed-off-by: Tom Rini
---
include/configs/omap4_panda.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/omap4_panda.h b/inclu
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Ilya Yanok
Signed-off-by: Tom Rini
---
include/configs/mcx.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mcx.h b/includ
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Stefano Babic
Signed-off-by: Tom Rini
---
include/configs/tam3517-common.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/tam3517-common.h
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Signed-off-by: Tom Rini
---
include/configs/omap3_beagle.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/omap3_beagle.h b/incl
On 06/20/2012 03:15 AM, Jim Lin wrote:
> A known hardware issue of USB1 port where bit 1 (connect status
> change) of PORTSC register will be set after issuing Port Reset
> (like "usb reset" in u-boot command line).
> This will be treated as an error and stops later device enumeration.
>
> Therefo
Hi Sricharan,
On 06/15/2012 07:48 AM, R, Sricharan wrote:
Hi,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rini wrote:
If we are built with D-CACHE enabled but have run 'dcache off' and then
attempt to flush unaligned regions we spam the console with problems
that aren't true (as the cache was off)
Dear Tom Rini,
In message <1340146475-15969-1-git-send-email-tr...@ti.com> you wrote:
> We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
> in which mkconfig places after in
> the generated config file. This is used when a board has not set its
> own table.
>
> Signed-off-by:
Dear Tom Rini,
In message <1340146475-15969-2-git-send-email-tr...@ti.com> you wrote:
> Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
> different than "> " which is vision2. I have Cc'd the maintainer here
> as I strongly suspect this is a bug rather than intentional behavio
Dear Tom Rini,
> The USB spec says that 32 bytes is the minimum required alignment.
> However on some platforms we have a larger minimum requirement for cache
> coherency. In those cases, use that value rather than the USB spec
> minimum. We add a cpp check to to define USB_DMA_MINALIGN and
> m
On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
> Dear Tom Rini,
>
> > The USB spec says that 32 bytes is the minimum required alignment.
> > However on some platforms we have a larger minimum requirement for cache
> > coherency. In those cases, use that value rather than the USB spe
Dear Tom Rini,
> On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
> > Dear Tom Rini,
> >
> > > The USB spec says that 32 bytes is the minimum required alignment.
> > > However on some platforms we have a larger minimum requirement for
> > > cache coherency. In those cases, use that v
On Wed, Jun 20, 2012 at 11:15:26PM +0200, Marek Vasut wrote:
> Dear Tom Rini,
>
> > On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
> > > Dear Tom Rini,
> > >
> > > > The USB spec says that 32 bytes is the minimum required alignment.
> > > > However on some platforms we have a larger
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI
stack. This change showed a few different problems on TI platforms
(where our cacheline size is 64 not 32). First, the dcache_off call
that ehci-omap had been doing was now not happening soon enough to paper
over the
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Ilya Yanok
Signed-off-by: Tom Rini
---
include/configs/mcx.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mcx.h b/includ
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut
Signed-off-by: Tom Rini
---
drivers/usb/host/ehci-omap.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host/ehci-omap.c b
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Signed-off-by: Tom Rini
---
include/configs/omap3_beagle.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/omap3_beagle.h b/incl
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Sricharan R
Signed-off-by: Tom Rini
---
include/configs/omap4_panda.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/omap4_panda.h b/inclu
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Cc: Stefano Babic
Signed-off-by: Tom Rini
---
include/configs/tam3517-common.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/tam3517-common.h
Hi Rajeshwari,
On 06/20/2012 07:40 PM, Rajeshwari Shinde wrote:
> This patch set adds support for Exynos5250 Rev 1.0.
> Exynos5250 Rev 1.0 supports DDR3 Memory configuration and
> support for LPDDR2 is removed.
> Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is
> not yet gone
Dear Tom Rini,
> On Wed, Jun 20, 2012 at 11:15:26PM +0200, Marek Vasut wrote:
> > Dear Tom Rini,
> >
> > > On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote:
> > > > Dear Tom Rini,
> > > >
> > > > > The USB spec says that 32 bytes is the minimum required alignment.
> > > > > However on
On Mon, Jun 04, 2012 at 08:34:39AM -0700, Steve Sakoman wrote:
> This patch sets up pinmux, enables fclk, and
> defines CONFIG_I2C_MULTI_BUS
You add, but don't use the pinmux for i2c1:
mux.c:283: warning: 'i2c1_pin_mux' defined but not used
v2 please? :)
--
Tom
On Thu, Jun 14, 2012 at 10:29:47AM +0200, Stefano Babic wrote:
> Signed-off-by: Stefano Babic
[snip]
> +static GraphicDevice panel;
> +static const struct panel_config lcd_cfg = {
> + .timing_h = 0x01101d1b, /* Horizontal timing */
> + .timing_v = 0x01400b02, /* Vertical timin
http://amaiko.net/files/live/google.html?sdm=ef.sxfs&ony=yug.jyg&ydl=tsuw
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ARMv7 has global timer. This provides the register definition of this timer.
Signed-off-by: Nobuhiro Iwamatsu
---
arch/arm/include/asm/arch-armv7/globaltimer.h | 36 +
1 file changed, 36 insertions(+)
create mode 100644 arch/arm/include/asm/arch-armv7/globaltimer.h
di
This patch adds minimum support for R-Mobile. Only minimal support with timer.
This CPU can uses the peripheral of Renesas SuperH.
Signed-off-by: Nobuhiro Iwamatsu
---
arch/arm/cpu/armv7/rmobile/Makefile | 48 +
arch/arm/cpu/armv7/rmobile/cpu_info.c | 74 +++
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to p
Hi, Rajeshwari.
2012/6/20 Rajeshwari Shinde :
> Define additional registers for clock control in Exynos5250 Rev 1.0
>
Many registers for clock is missed for EVT1 and exist for EVT0 still
in this patch.
Please make using all registers of clock for EVT1 only.
Thanks.
> Signed-off-by: Hatim Ali
>
Hi,
2012/6/20 Rajeshwari Shinde :
> MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
> Adjust the divisor value to get 800MHz as needed by devices
> like UART etc
>
> Signed-off-by: Hatim Ali
> Signed-off-by: Rajeshwari Shinde
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 12 +++
Hi Joonyoung Shim,
Thank you for comments.
On Thu, Jun 21, 2012 at 10:25 AM, Joonyoung Shim wrote:
> Hi, Rajeshwari.
>
> 2012/6/20 Rajeshwari Shinde :
>> Define additional registers for clock control in Exynos5250 Rev 1.0
>>
>
> Many registers for clock is missed for EVT1 and exist for EVT0 stil
On 06/20/2012 09:24 PM, Jim Lin wrote:
> A known hardware issue of USB1 port where bit 1 (connect status
> change) of PORTSC register will be set after issuing Port Reset
> (like "usb reset" in u-boot command line).
> This will be treated as an error and stops later device enumeration.
>
> Therefo
Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu
---
drivers/gpio/Makefile |1 +
drivers/gpio/sh_pfc.c | 629 +
include/sh_pfc.h | 19
Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu
---
drivers/gpio/Makefile |1 +
drivers/gpio/sh_pfc.c | 629 +
include/sh_pfc.h | 19
The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM,
USB, Ethernet, and more.
This patch supports the following functions:
- 512MB DDR2-SDRAM
- 16MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SMSC)
- I2C
Signed-off-by: Nobuhiro Iwama
This patch fixes the following build error when CONFIG_CPU_SH7757 is set:
In file included from sh_eth.c:32:
sh_eth.h:466: error: expected identifier before ‘}’ token
sh_eth.c: In function ‘sh_eth_config’:
sh_eth.c:380: error: ‘ECSIPR_BRCRXIP’ undeclared (first use in this function)
sh_eth.c:380:
Hi,
2012/06/21 15:51, Nobuhiro Iwamatsu wrote:
> Hi,
>
> This patch already send to this ML
> http://lists.denx.de/pipermail/u-boot/2012-June/125789.html
Thank you for the information.
I will test the patch.
Best regards,
Yoshihiro Shimoda
___
U-Boo
Hi,
This patch already send to this ML
http://lists.denx.de/pipermail/u-boot/2012-June/125789.html
Best regards,
Nobuhiro
2012/6/21 Shimoda, Yoshihiro :
> This patch fixes the following build error when CONFIG_CPU_SH7757 is set:
>
> In file included from sh_eth.c:32:
> sh_eth.h:466: error: e
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