Wolfgang,
Please ignore the patch, I will resend it in the next patch sets.
Sorry for that.
Thanks,
Dave
> -Original Message-
> From: Liu Dave-R63238
> Sent: 2008?11?21? 7:51 AM
> To: u-boot@lists.denx.de
> Cc: [EMAIL PROTECTED]; Liu Dave-R63238
> Subject: [PATCH] fsl-ddr: update the b
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.
Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 12
1 files changed, 8 insertions(+), 4 deletions(-)
diff
- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support
Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 24 +---
include/asm-ppc/fsl_ddr_sdram.h |3 +++
2 files changed, 16 insertions(+), 11 d
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.
If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued t
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
---
board/freescale/mpc8540ads/ddr.c |3 +++
board/freescale/mpc8544ds/ddr.c
The wake up ARP feature need use the memory to process
wake up packet, we enable auto self refresh to support it.
Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
---
board/freescale/mpc8536ds/ddr.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8536ds
On Thursday 20 November 2008, Dave Mitchell wrote:
> Expanded OCM TLB to allow access to 64K OCM as well as 256K of
> internal SRAM.
>
> Adjusted internal SRAM initialization to match updated user
> manual recommendation.
>
> OCM & ISRAM are now mapped as follows:
> physicalvirtual
Anybody interested in the patch?
- Original Message -
From: "Valeriy Glushkov" <[EMAIL PROTECTED]>
To:
Sent: 18 ?? 2008 ?. 19:27
Subject: [U-Boot] [PATCH] NAND: fixed bugs in nand_[read,write]_skip_bad()
>- fixed bugs in nand_[read,write]_skip_bad() to double speed
> - added printi
> A 4xx FP toolchain is a perfectly good idea - that's why we
> support such a configuration in ppc_4xxFP with the ELDK. But
> it doesn't need any changes to U-Boot.
I tried building u-boot with the 4xxFP toolchain from ELDK and -
surprise, surprise - it worked.
So there is definetly somet
On Nov 21, 2008, at 2:31 AM, Dave Liu wrote:
> The wake up ARP feature need use the memory to process
> wake up packet, we enable auto self refresh to support it.
>
> Signed-off-by: Dave Liu <[EMAIL PROTECTED]>
> ---
> board/freescale/mpc8536ds/ddr.c |6 ++
> 1 files changed, 6 insertions(
The following changes since commit 9b827cf1720acda2473afa516956eab6f7cca9a1:
Selvamuthukumar (1):
Align end of bss by 4 bytes
are available in the git repository at:
git://www.denx.de/git/u-boot-ppc4xx.git master
Dave Mitchell (2):
ppc4xx: Added ppc4xx-isram.h for internal SRAM
On Thursday 20 November 2008, Steven A. Falco wrote:
> The definitions of bits in SDR_CFG are incorrect, and not used within
> U-Boot. Therefore, they can be removed.
>
> The naming of the sdr_ddrdl/sdr_cfg registers do not follow conventions,
> and are unused, so they can be removed too.
>
> A de
On Thursday 20 November 2008, Dave Mitchell wrote:
> Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
> L2 cache DCRs from ppc440.h to this new header.
>
> Also converted these DCR defines from lowercase to uppercase and
> modified referencing modules to use them.
>
> Signed-off-by:
On Friday 14 November 2008, Yuri Tikhonov wrote:
> Hello,
>
Please remove this "Hello," from the commit text next time.
> This patch enables support for EXT2, and increases the
> CONFIG_SYS_BOOTMAPSZ size for the default configuration
> of the katmai boards to use them as the RAID-reference
> A
Hi Matthias,
I just noticed that PCI405 doesn't build anymore in the current U-Boot
repository (main and ppc4xx):
[EMAIL PROTECTED] u-boot-ppc4xx (master)]$ ./MAKEALL PCI405
Configuring for PCI405 board...
ppc_4xx-objcopy: u-boot.bin: Bad value
ppc_4xx-objcopy: u-boot.bin: Bad value
make: *** [u
Hi Pieter,
I just noticed that the alpr doesn't build anymore in the current U-Boot
version (main and 4xx). The image size (256k) is exceeded because of general
code growth. We either need to remove some features/commands from the alpr
target or increase the image size. Please advise how to fix
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
---
board/ml2/u-boot.lds |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds
index 28c6546..13ceea0 100644
--- a/board/ml2/u-boot.lds
+++ b/board/ml2/u-boot.lds
@@ -63,7 +63,6 @@ SECTIO
Hi all,
we have trouble with the eth based config pins (ETH0...ETH6) of the MPC5200B
CPU. These pins act as the interface to an external phy and also act as
configurations pins to configure the size of the flash and other things.
While the reset is active these pins should be in their high impe
> -Original Message-
> From: Kumar Gala [mailto:[EMAIL PROTECTED]
> Sent: Friday, November 21, 2008 7:43 PM
> To: Liu Dave-R63238
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH 5/5] 85xx: enable the auto self
> refresh for wake up ARP
>
>
> On Nov 21, 2008, at 2:31 AM, Dav
After I looked into disassembled ARM codes, found no reason to cause
problem.
When I compiled with -Os option, the C source code like following:
static int flash_toggle (flash_info_t * info, flash_sect_t sect,
uint offset, uchar cmd)
{
void *addr;
cfiwor
Juergen, I haven't seen this behaviour. Have you asked you Freescale FAE?
Hey John, have you ever seen this sort of issue?
g.
On Fri, Nov 21, 2008 at 5:36 AM, Juergen Beisert <[EMAIL PROTECTED]> wrote:
> Hi all,
>
> we have trouble with the eth based config pins (ETH0...ETH6) of the MPC5200B
>
Hi Grant,
On Freitag, 21. November 2008, Grant Likely wrote:
> Juergen, I haven't seen this behaviour. Have you asked you Freescale FAE?
Yes. But no answer yet. Thats why I ask here.
Regards,
Juergen
--
Dipl.-Ing. Juergen Beisert | http://www.pengutronix.de
Pengutronix - Linux Solutions for
On Nov 21, 2008, at 6:20 AM, Liu Dave wrote:
>
>
>> -Original Message-
>> From: Kumar Gala [mailto:[EMAIL PROTECTED]
>> Sent: Friday, November 21, 2008 7:43 PM
>> To: Liu Dave-R63238
>> Cc: u-boot@lists.denx.de
>> Subject: Re: [U-Boot] [PATCH 5/5] 85xx: enable the auto self
>> refresh for
2008/11/20 Wolfgang Denk <[EMAIL PROTECTED]>:
> Dear "Simon Boman",
>
> In message <[EMAIL PROTECTED]> you wrote:
>>
>> I'm quite sure about kernel, the only interface I am going to use is
>> the serial interface.
>
> early debug?
>
>> Do you know where I can find the file where maps the U-boot cod
Jürgen,
Have a look at the manual chapter 4 (=Reset + Config).
SRESET (issued by gpt0 - watchdog) isn't supposed to do a full hardware
reset.
Looks like you should make use of the SRESET and trigger HRESET accordingly.
I could solve this with _not_ using the internal watchdog but an
external on
Simon Boman wrote:
> 2008/11/20 Wolfgang Denk <[EMAIL PROTECTED]>:
>> Dear "Simon Boman",
[snip]
>
> Thank you for your help, I find your example at your site
> http://www.denx.de/wiki/DULG/DecodingUBootCrashDumps which was great!
>
> Now I have got find where the U-boot goes wrong:
>
> FDT_ER
Hi Andre,
On Freitag, 21. November 2008, Andre Schwarz wrote:
> Have a look at the manual chapter 4 (=Reset + Config).
> SRESET (issued by gpt0 - watchdog) isn't supposed to do a full hardware
> reset.
> Looks like you should make use of the SRESET and trigger HRESET
> accordingly.
>
> I could sol
2008/11/21 Jerry Van Baren <[EMAIL PROTECTED]>:
> Simon Boman wrote:
>>
>> 2008/11/20 Wolfgang Denk <[EMAIL PROTECTED]>:
>>>
>>> Dear "Simon Boman",
>
> [snip]
>
>>
>> Thank you for your help, I find your example at your site
>> http://www.denx.de/wiki/DULG/DecodingUBootCrashDumps which was great!
On Tue, Nov 18, 2008 at 07:27:29PM +0200, Valeriy Glushkov wrote:
> - fixed bugs in nand_[read,write]_skip_bad() to double speed
Changelog should specify what the bugs are.
> - added printing of dots to show progress
>
> Signed-off-by: Valeriy Glushkov <[EMAIL PROTECTED]>
> ---
> drivers/mtd/na
Fix merge error.
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Jean-Christophe: Regarding
http://lists.denx.de/pipermail/u-boot/2008-November/043711.html
this is the only issue I can find in omap3.h. It doesn't seem to me
that you removed anything (??)
Current u-boot-arm/omap3 head (b8220
Becky Bruce wrote:
> I made some updates to the code that didn't make it into the
> README - fix this
>
> Signed-off-by: Becky Bruce <[EMAIL PROTECTED]>
Applied to u-boot-mpc86xx.
Thanks,
jdl
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Hi
I have a custom ppc405ep board with 128MB SDRAM, very similar to the
AMCC Taihu board. U-Boot 1.1.4 works perfectly fine. But version 1.3.4
freezes after saying "Relocating now" in debug mode.
Additionally, I've observed a strange effect concerning memory size:
When a BDI2000 emulator is conne
Currently the size parameters of the UBI commands (e.g. "ubi write") are
decoded as
decimal instead of hex as default. This patch now interprets all these values
consistantly as hex, as all other standard U-Boot commands do.
Signed-off-by: Stefan Roese <[EMAIL PROTECTED]>
---
This depends on the
Hi Stefan,
you are right. U-Boot has grown a little bit and for PCI405 it blasted the
192k limit. I cannot just increase the U-Boot size for this board, so I
removed some unneeded code and features. I need to do
some more testing with the stripped down configuration.
I will post a patch at the
In message <[EMAIL PROTECTED]> you wrote:
> Currently the size parameters of the UBI commands (e.g. "ubi write") are
> decoded as
> decimal instead of hex as default. This patch now interprets all these values
> consistantly as hex, as all other standard U-Boot commands do.
You may want to rephr
Taken all the duplicated code for enabling common modules and apply
software workarounds from the board specific code into common
functions. Also added comments explaining the workarounds
(from TI errata documents) and replaced some numerical bit numbers
with more meaningful defines.
Signed-off-by
Signed Off By: Graeme Russ <[EMAIL PROTECTED]>
---
Split '[U-Boot] [PATCH 2/2] Minor changes to allow clean creation of new
i386/sc520 boards' as requested
cpu/i386/sc520.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 8bcb97
Signed Off By: Graeme Russ <[EMAIL PROTECTED]>
---
Split '[U-Boot] [PATCH 2/2] Minor changes to allow clean creation of new
i386/sc520 boards' as requested
include/asm-i386/ic/pci.h | 49 +++
include/asm-i386/ic/sc520.h | 22 ---
2 f
On 18:28 Fri 21 Nov , Dirk Behme wrote:
> Fix merge error.
>
> Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
>
> ---
apply to u-boot-arm/omap3
>
> Jean-Christophe: Regarding
>
> http://lists.denx.de/pipermail/u-boot/2008-November/043711.html
>
> this is the only issue I can find in omap3.h
In response to my own email:
> I did not see this when I built before submitting my patch. It seems to build
> fine using ELDK version 4.1. I just tried building with 4.2 and am
> seeing the errors that you described. For some reason, the 4.2 build has
> about 48 extra bytes to it, and is once
From: Becky Bruce <[EMAIL PROTECTED]>
The current code will cause the creation of a 4GB window
starting at 0 if we have more than 4GB of RAM installed,
which overlaps with PCI_MEM space and causes pci_bus_to_phys()
to return erroneous information. Limit the size to 4GB - 1;
which causes the code t
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