Dear Kyle Moffett,
In message <1298478920-22044-1-git-send-email-kyle.d.moff...@boeing.com> you
wrote:
> The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
> integer divide operations to convert between nanoseconds and DDR clock
> cycles given arbitrary DDR clock frequencies.
On Feb 23, 2011, at 10:35 AM, Kyle Moffett wrote:
> The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
> integer divide operations to convert between nanoseconds and DDR clock
> cycles given arbitrary DDR clock frequencies.
>
> Since all of the inputs to this are 32-bit (nan
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
> The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
> integer divide operations to convert between nanoseconds and DDR clock
> cycles given arbitrary DDR clock frequencies.
>
> Since all of the inputs to this are 32-bit (
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
> + * Now divide by 5^12 and track the 32-bit remainder, then divide
> + * by 2*(2^12) using shifts (and updating the remainder).
> + */
> + clks_rem = do_div(clks, UL_5pow12);
> + clks_rem <<= 13;
Shouldn't this be clks
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
> The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
> integer divide operations to convert between nanoseconds and DDR clock
> cycles given arbitrary DDR clock frequencies.
>
> Since all of the inputs to this are 32-bit (
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