On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote: > The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit > integer divide operations to convert between nanoseconds and DDR clock > cycles given arbitrary DDR clock frequencies. > > Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, > and DDR frequencies), we can easily restructure the computation to use > the "do_div()" function to perform 64-bit/32-bit divide operations. > > This decreases compute time rather significantly for each conversion and > avoids bringing in a very complicated function from libgcc. > > It should be noted that nothing else in U-Boot or the Linux kernel seems > to require a full 64-bit divide on any 32-bit PowerPC. > > Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection. > > Signed-off-by: Kyle Moffett <kyle.d.moff...@boeing.com> > Cc: Andy Fleming <aflem...@gmail.com> > Cc: Kumar Gala <kumar.g...@freescale.com> > Cc: Wolfgang Denk <w...@denx.de> > Cc: Kim Phillips <kim.phill...@freescale.com> > ---
Acked-by: York Sun <york...@freescale.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
