Re: [U-Boot] [U-Boot,3/4] rockchip: clk: update dwmmc clock div

2017-07-27 Thread Dr. Philipp Tomsich
> On 27 Jul 2017, at 05:29, Kever Yang wrote: > > Philipp, > > > On 07/27/2017 02:01 AM, Philipp Tomsich wrote: >> >> >> On Wed, 26 Jul 2017, Kever Yang wrote: >> >>> dwmmc controller has default internal divider by 2, >>> sync code for all Rockchip SoC with: >>> 4055b46 rockchip: clk: rk32

Re: [U-Boot] [U-Boot,3/4] rockchip: clk: update dwmmc clock div

2017-07-26 Thread Kever Yang
Philipp, On 07/27/2017 02:01 AM, Philipp Tomsich wrote: On Wed, 26 Jul 2017, Kever Yang wrote: dwmmc controller has default internal divider by 2, sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting While I know that this is the case (i.e. we measured

Re: [U-Boot] [U-Boot,3/4] rockchip: clk: update dwmmc clock div

2017-07-26 Thread Philipp Tomsich
On Wed, 26 Jul 2017, Kever Yang wrote: dwmmc controller has default internal divider by 2, sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting While I know that this is the case (i.e. we measured the output frequencies a while back), we should add some

Re: [U-Boot] [U-Boot,3/4] rockchip: clk: update dwmmc clock div

2017-07-26 Thread Philipp Tomsich
> dwmmc controller has default internal divider by 2, > sync code for all Rockchip SoC with: > 4055b46 rockchip: clk: rk3288: fix mmc clock setting > > Signed-off-by: Kever Yang > --- > > drivers/clk/rockchip/clk_rk3036.c | 6 +++--- > drivers/clk/rockchip/clk_rk3188.c | 4 ++-- > drivers/clk