Hi Tom/Simon/Febio,
On 17 November 2015 at 02:37, Simon Glass wrote:
> Hi Tom,
>
> On 15 November 2015 at 18:58, Tom Rini wrote:
>> On Sun, Nov 15, 2015 at 06:34:51PM -0700, Simon Glass wrote:
>>> Hi,
>>>
>>> On 13 November 2015 at 03:41, Bin Meng wrote:
>>> > Hi,
>>> >
>>> > On Wed, Nov 11, 20
Hi Tom,
On 15 November 2015 at 18:58, Tom Rini wrote:
> On Sun, Nov 15, 2015 at 06:34:51PM -0700, Simon Glass wrote:
>> Hi,
>>
>> On 13 November 2015 at 03:41, Bin Meng wrote:
>> > Hi,
>> >
>> > On Wed, Nov 11, 2015 at 10:04 PM, Fabio Estevam wrote:
>> >> On Wed, Nov 11, 2015 at 12:56 AM, Simon
Hi Simon,
On Sun, Nov 15, 2015 at 11:34 PM, Simon Glass wrote:
> Fabio can you please rework this to remove the pre-driver-model
> support, and add your new functions to struct dm_spi_flash_ops
> instead, then convert the affected boards to driver model?
Ok, I will give it a try in converting i
On Sun, Nov 15, 2015 at 06:34:51PM -0700, Simon Glass wrote:
> Hi,
>
> On 13 November 2015 at 03:41, Bin Meng wrote:
> > Hi,
> >
> > On Wed, Nov 11, 2015 at 10:04 PM, Fabio Estevam wrote:
> >> On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
> >>> Hi Fabio,
> >>>
> >>> On 10 November 2015 a
Hi,
On 13 November 2015 at 03:41, Bin Meng wrote:
> Hi,
>
> On Wed, Nov 11, 2015 at 10:04 PM, Fabio Estevam wrote:
>> On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
>>> Hi Fabio,
>>>
>>> On 10 November 2015 at 16:51, Fabio Estevam wrote:
Hi Simon,
On Tue, Nov 10, 2015
Hi,
On Wed, Nov 11, 2015 at 10:04 PM, Fabio Estevam wrote:
> On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
>> Hi Fabio,
>>
>> On 10 November 2015 at 16:51, Fabio Estevam wrote:
>>>
>>> Hi Simon,
>>>
>>> On Tue, Nov 10, 2015 at 10:09 PM, Simon Glass wrote:
>>>
>>> > This patch breaks chr
On Thu, Nov 12, 2015 at 12:25 AM, Jagan Teki wrote:
> On 11 November 2015 at 15:13, Fabio Estevam wrote:
>> On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
>>
>>> It crashes reading the environment:
>>>
>>> U-Boot 2015.10-00544-gcad0499 (Nov 10 2015 - 17:06:00 -0700)
>>>
>>> CPU: Intel(R)
On 11 November 2015 at 15:13, Fabio Estevam wrote:
> On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
>
>> It crashes reading the environment:
>>
>> U-Boot 2015.10-00544-gcad0499 (Nov 10 2015 - 17:06:00 -0700)
>>
>> CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz
>> DRAM: 2.7 GiB
>> SF: Dete
On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
> Hi Fabio,
>
> On 10 November 2015 at 16:51, Fabio Estevam wrote:
>>
>> Hi Simon,
>>
>> On Tue, Nov 10, 2015 at 10:09 PM, Simon Glass wrote:
>>
>> > This patch breaks chromebook_link - I think because it adds a new
>> > operation which is not
On Wed, Nov 11, 2015 at 12:56 AM, Simon Glass wrote:
> It crashes reading the environment:
>
> U-Boot 2015.10-00544-gcad0499 (Nov 10 2015 - 17:06:00 -0700)
>
> CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz
> DRAM: 2.7 GiB
> SF: Detected W25Q64CV with page size 256 Bytes, erase size 4 KiB, tota
Hi Fabio,
On 10 November 2015 at 16:51, Fabio Estevam wrote:
>
> Hi Simon,
>
> On Tue, Nov 10, 2015 at 10:09 PM, Simon Glass wrote:
>
> > This patch breaks chromebook_link - I think because it adds a new
> > operation which is not supported by all flash chips. Those that are
> > not supported (i
Hi Simon,
On Tue, Nov 10, 2015 at 10:09 PM, Simon Glass wrote:
> This patch breaks chromebook_link - I think because it adds a new
> operation which is not supported by all flash chips. Those that are
> not supported (i.e that don't have the 'flash_is_locked' method)
> should still work.
What i
On Tue, Nov 10, 2015 at 04:09:52PM -0800, Simon Glass wrote:
> Hi Fabio,
>
> On 6 November 2015 at 04:24, Tom Rini wrote:
> > On Thu, Nov 05, 2015 at 12:43:42PM -0200, Fabio Estevam wrote:
> >
> >> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
> >> status register that can prote
Hi Fabio,
On 6 November 2015 at 04:24, Tom Rini wrote:
> On Thu, Nov 05, 2015 at 12:43:42PM -0200, Fabio Estevam wrote:
>
>> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
>> status register that can protect selected regions of the SPI NOR.
>>
>> Take these bits into account when
On Thu, Nov 05, 2015 at 12:43:42PM -0200, Fabio Estevam wrote:
> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
> status register that can protect selected regions of the SPI NOR.
>
> Take these bits into account when performing erase operations,
> making sure that the protected
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.
Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.
Tested on a mx6qsabresd:
=> sf probe
SF: Detected M25
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