On 14 July 2016 at 21:20, Simon Glass wrote:
> Hi Ziyuan,
>
> On 14 July 2016 at 09:43, Ziyuan Xu wrote:
>> Hi Simon,
>>
>>
>> On 2016年07月14日 23:00, Simon Glass wrote:
>>>
>>> On 12 July 2016 at 19:06, Ziyuan Xu wrote:
On 2016年07月12日 20:59, Simon Glass wrote:
>
> Hi Ziyuan
Hi Ziyuan,
On 14 July 2016 at 09:43, Ziyuan Xu wrote:
> Hi Simon,
>
>
> On 2016年07月14日 23:00, Simon Glass wrote:
>>
>> On 12 July 2016 at 19:06, Ziyuan Xu wrote:
>>>
>>>
>>> On 2016年07月12日 20:59, Simon Glass wrote:
Hi Ziyuan,
On 6 July 2016 at 03:34, Ziyuan Xu wrote:
>
>
Hi Simon,
On 2016年07月14日 23:00, Simon Glass wrote:
On 12 July 2016 at 19:06, Ziyuan Xu wrote:
On 2016年07月12日 20:59, Simon Glass wrote:
Hi Ziyuan,
On 6 July 2016 at 03:34, Ziyuan Xu wrote:
From: Xu Ziyuan
Invalidate dcache before starting the DMA to ensure coherency. In case
there are an
On 12 July 2016 at 19:06, Ziyuan Xu wrote:
>
>
> On 2016年07月12日 20:59, Simon Glass wrote:
>>
>> Hi Ziyuan,
>>
>> On 6 July 2016 at 03:34, Ziyuan Xu wrote:
>>>
>>> From: Xu Ziyuan
>>>
>>> Invalidate dcache before starting the DMA to ensure coherency. In case
>>> there are any dirty lines from the
On 2016年07月12日 20:59, Simon Glass wrote:
Hi Ziyuan,
On 6 July 2016 at 03:34, Ziyuan Xu wrote:
From: Xu Ziyuan
Invalidate dcache before starting the DMA to ensure coherency. In case
there are any dirty lines from the DMA buffer in the cache, subsequent
cache-line replacements may corrupt th
Hi Ziyuan,
On 6 July 2016 at 03:34, Ziyuan Xu wrote:
> From: Xu Ziyuan
>
> Invalidate dcache before starting the DMA to ensure coherency. In case
> there are any dirty lines from the DMA buffer in the cache, subsequent
> cache-line replacements may corrupt the buffer in memory while the DMA
> is
From: Xu Ziyuan
Invalidate dcache before starting the DMA to ensure coherency. In case
there are any dirty lines from the DMA buffer in the cache, subsequent
cache-line replacements may corrupt the buffer in memory while the DMA
is still going on. Cache-line replacement can happen if the CPU trie
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