Hi Ziyuan, On 6 July 2016 at 03:34, Ziyuan Xu <xzy...@rock-chips.com> wrote: > From: Xu Ziyuan <xzy...@rock-chips.com> > > Invalidate dcache before starting the DMA to ensure coherency. In case > there are any dirty lines from the DMA buffer in the cache, subsequent > cache-line replacements may corrupt the buffer in memory while the DMA > is still going on. Cache-line replacement can happen if the CPU tries to > bring some other memory locations into the cache while the DMA is going > on. > > Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com> > --- > > Changes in v3: > - New commit since v3 to fix the coherence issue between memory and > cache > > Changes in v2: None > > drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c > b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c > index 12f5c85..0d6d2fb 100644 > --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c > +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c > @@ -110,6 +110,9 @@ static int setdma_rx(struct dwc2_ep *ep, struct > dwc2_request *req) > > ctrl = readl(®->out_endp[ep_num].doepctl); > > + invalidate_dcache_range((unsigned long) ep->dma_buf, > + (unsigned long) ep->dma_buf + ep->len);
There is an invalidate in complete_rx() which is one of the callers for this function. It seems to me that we should not have this in two places. Why do we have this problem? Is it because the other calls to setdma_rx() don't invalidate? I think the invalidate should happen just before reading the data. Can you please check if the other invalidate is needed? Also see how it cache-aligns the end address. > + > writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); > writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), > ®->out_endp[ep_num].doeptsiz); > -- > 1.9.1 > > Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot