Re: [U-Boot] [PATCH v3] mx6: Enable L2 cache support

Hi Stefano, On Wed, Jan 29, 2014 at 10:47 AM, Stefano Babic wrote: > Hi Dirk, > > On 28/01/2014 17:53, Dirk Behme wrote: > >> >> Just for better understanding: Do you want to keep this intentionally >> simple? Or is there any special reason why you don't set additional >> (performance) registers

Re: [U-Boot] [PATCH v3] mx6: Enable L2 cache support

Hi Dirk, On 28/01/2014 17:53, Dirk Behme wrote: > > Just for better understanding: Do you want to keep this intentionally > simple? Or is there any special reason why you don't set additional > (performance) registers here? E.g. the L2 PREFETCH and POWER registers, > and the tag and data latency

Re: [U-Boot] [PATCH v3] mx6: Enable L2 cache support

Hi Dirk, On Tue, Jan 28, 2014 at 2:53 PM, Dirk Behme wrote: > Just for better understanding: Do you want to keep this intentionally > simple? Or is there any special reason why you don't set additional > (performance) registers here? E.g. the L2 PREFETCH and POWER registers, and > the tag and da

Re: [U-Boot] [PATCH v3] mx6: Enable L2 cache support

Hi Fabio, Am 28.01.2014 15:54, schrieb Fabio Estevam: Add L2 cache support and enable it by default. Signed-off-by: Fabio Estevam --- Changes since v2: - Add L2_PL310_BASE definition in imx_regs.h Changes since v1: - Fx typo in commit log arch/arm/cpu/armv7/mx6/soc.c | 20 ++

Re: [U-Boot] [PATCH v3] mx6: Enable L2 cache support

On 28/01/2014 15:54, Fabio Estevam wrote: > Add L2 cache support and enable it by default. > > Signed-off-by: Fabio Estevam > --- > Changes since v2: > - Add L2_PL310_BASE definition in imx_regs.h > Changes since v1: > - Fx typo in commit log > > arch/arm/cpu/armv7/mx6/soc.c | 20 ++

[U-Boot] [PATCH v3] mx6: Enable L2 cache support

Add L2 cache support and enable it by default. Signed-off-by: Fabio Estevam --- Changes since v2: - Add L2_PL310_BASE definition in imx_regs.h Changes since v1: - Fx typo in commit log arch/arm/cpu/armv7/mx6/soc.c | 20 arch/arm/include/asm/arch-mx6/imx-regs.h |