Hi Fabio, Am 28.01.2014 15:54, schrieb Fabio Estevam:
Add L2 cache support and enable it by default.Signed-off-by: Fabio Estevam <fabio.este...@freescale.com> --- Changes since v2: - Add L2_PL310_BASE definition in imx_regs.h Changes since v1: - Fx typo in commit log arch/arm/cpu/armv7/mx6/soc.c | 20 ++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + include/configs/mx6_common.h | 5 +++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba..b84de87 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,6 +8,8 @@ */ #include <common.h> +#include <asm/armv7.h> +#include <asm/pl310.h> #include <asm/errno.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> @@ -336,3 +338,21 @@ void imx_setup_hdmi(void) writel(reg, &mxc_ccm->chsccdr); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define L2CACHE 1 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + setbits_le32(&pl310->pl310_ctrl, L2CACHE); + +}
Just for better understanding: Do you want to keep this intentionally simple? Or is there any special reason why you don't set additional (performance) registers here? E.g. the L2 PREFETCH and POWER registers, and the tag and data latency settings? Like done in the kernel.
Best regards Dirk _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
