Hi Jaehoon,
On 30/01/2018 06:17, Jaehoon Chung wrote:
Hi JJ,
On 01/25/2018 07:51 PM, Jean-Jacques Hiblot wrote:
This series adds the missing bits to enable the UHS and HS200 modes
for the TI platforms.
Enabling support for high speed modes on omap5 requires implementing:
* io signal voltag
Hi JJ,
On 01/25/2018 07:51 PM, Jean-Jacques Hiblot wrote:
>
> This series adds the missing bits to enable the UHS and HS200 modes
> for the TI platforms.
>
> Enabling support for high speed modes on omap5 requires implementing:
> * io signal voltage selection
> * tuning support
> * pin config
On 29/01/2018 05:45, Lokesh Vutla wrote:
On Thursday 25 January 2018 04:21 PM, Jean-Jacques Hiblot wrote:
This series adds the missing bits to enable the UHS and HS200 modes
for the TI platforms.
For my understanding, these patches enable HS modes only in U-Boot
proper or in SPL also?
Enabli
On Thursday 25 January 2018 04:21 PM, Jean-Jacques Hiblot wrote:
>
> This series adds the missing bits to enable the UHS and HS200 modes
> for the TI platforms.
For my understanding, these patches enable HS modes only in U-Boot
proper or in SPL also?
Thanks and regards,
Lokesh
>
> Enabling s
Hi JJ,
On 01/25/2018 07:51 PM, Jean-Jacques Hiblot wrote:
>
> This series adds the missing bits to enable the UHS and HS200 modes
> for the TI platforms.
>
> Enabling support for high speed modes on omap5 requires implementing:
> * io signal voltage selection
> * tuning support
> * pin config
This series adds the missing bits to enable the UHS and HS200 modes
for the TI platforms.
Enabling support for high speed modes on omap5 requires implementing:
* io signal voltage selection
* tuning support
* pin configuration (IO delays)
The few last patches enable the high speed modes for t
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