Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-21 Thread Marek Vasut
On 09/21/2016 03:53 AM, Chin Liang See wrote: > On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote: >> On 09/20/2016 08:05 AM, Chin Liang See wrote: >>> To enable configuration of sdr.ctrlcfg.extratime1 register which >>> enable >>> extra clocks for read to write command timing. This is critical

Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Chin Liang See
On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote: > On 09/20/2016 08:05 AM, Chin Liang See wrote: > > To enable configuration of sdr.ctrlcfg.extratime1 register which > > enable > > extra clocks for read to write command timing. This is critical to > > ensure successful LPDDR2 interface > > >

Re: [U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Marek Vasut
On 09/20/2016 08:05 AM, Chin Liang See wrote: > To enable configuration of sdr.ctrlcfg.extratime1 register which enable > extra clocks for read to write command timing. This is critical to > ensure successful LPDDR2 interface > > Signed-off-by: Chin Liang See > Cc: Marek Vasut > Cc: Dinh Nguyen

[U-Boot] [PATCH v2] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See
To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen --- Changes for v2 - Removed v1 patches #2 to #9 as no boar