On Wednesday 14 March 2012 17:04:32 Eric Nelson wrote:
> You want I should send a formal patch?
yes please
> Should I consider "looks fine" to be an ack?
i'll post an acked-by tag to that and then patchwork will do the right thing
for people to track
-mike
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On 03/14/2012 01:33 PM, Mike Frysinger wrote:
On Wednesday 14 March 2012 15:12:10 Eric Nelson wrote:
On 03/13/2012 10:41 PM, Mike Frysinger wrote:
On Wednesday 14 March 2012 01:12:38 Eric Nelson wrote:
Most of the PPC devices seem to have values of 16 or 32
for ARCH_DMA_MINALIGN, but PPC64BRID
On Wednesday 14 March 2012 15:12:10 Eric Nelson wrote:
> On 03/13/2012 10:41 PM, Mike Frysinger wrote:
> > On Wednesday 14 March 2012 01:12:38 Eric Nelson wrote:
> >> Most of the PPC devices seem to have values of 16 or 32
> >> for ARCH_DMA_MINALIGN, but PPC64BRIDGE and E500MC would
> >> have a pro
On 03/13/2012 10:41 PM, Mike Frysinger wrote:
On Wednesday 14 March 2012 01:12:38 Eric Nelson wrote:
Most of the PPC devices seem to have values of 16 or 32
for ARCH_DMA_MINALIGN, but PPC64BRIDGE and E500MC would
have a problem if their drivers don't implement a bounce
buffer because PKTALIGN<
On Wednesday 14 March 2012 01:12:38 Eric Nelson wrote:
> Most of the PPC devices seem to have values of 16 or 32
> for ARCH_DMA_MINALIGN, but PPC64BRIDGE and E500MC would
> have a problem if their drivers don't implement a bounce
> buffer because PKTALIGN < ARCH_DMA_MINALIGN.
>
> (see arch/powerpc
Dear Eric Nelson,
> On 03/13/2012 06:43 PM, Marek Vasut wrote:
> > Dear Mike Frysinger,
> >
> >> On Tuesday 13 March 2012 14:42:29 Eric Nelson wrote:
> >>> On 03/13/2012 07:41 AM, Mike Frysinger wrote:
> On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
> > --- a/drivers/net/fec_mxc.c
On 03/13/2012 06:43 PM, Marek Vasut wrote:
Dear Mike Frysinger,
On Tuesday 13 March 2012 14:42:29 Eric Nelson wrote:
On 03/13/2012 07:41 AM, Mike Frysinger wrote:
On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
+#if ARCH_DMA_MINAL
Dear Eric Nelson,
> ensure that transmit and receive buffers are cache-line aligned
> invalidate cache for each packet as received
> update receive buffer descriptors one cache line at a time
> flush cache before transmitting
>
> Original patch by Marek:
> http:/
Dear Eric Nelson,
> On 03/13/2012 07:04 AM, Eric Nelson wrote:
> > ensure that transmit and receive buffers are cache-line aligned
> >
> > invalidate cache for each packet as received
> >
> > update receive buffer descriptors one cache line at a time
> >
> >
Dear Mike Frysinger,
> On Tuesday 13 March 2012 14:42:29 Eric Nelson wrote:
> > On 03/13/2012 07:41 AM, Mike Frysinger wrote:
> > > On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
> > >> --- a/drivers/net/fec_mxc.c
> > >> +++ b/drivers/net/fec_mxc.c
> > >>
> > >> +#if ARCH_DMA_MINALIGN> CON
Dear Eric Nelson,
> Thanks Mike,
>
> On 03/13/2012 07:41 AM, Mike Frysinger wrote:
> > On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
> >> --- a/drivers/net/fec_mxc.c
> >> +++ b/drivers/net/fec_mxc.c
> >>
> >> +#if ARCH_DMA_MINALIGN> CONFIG_SYS_CACHELINE_SIZE
> >> +#define CONFIG_FEC_ALIG
On Tuesday 13 March 2012 14:42:29 Eric Nelson wrote:
> On 03/13/2012 07:41 AM, Mike Frysinger wrote:
> > On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
> >> --- a/drivers/net/fec_mxc.c
> >> +++ b/drivers/net/fec_mxc.c
> >>
> >> +#if ARCH_DMA_MINALIGN> CONFIG_SYS_CACHELINE_SIZE
> >> +#define
Thanks Mike,
On 03/13/2012 07:41 AM, Mike Frysinger wrote:
On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
+#if ARCH_DMA_MINALIGN> CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_FEC_ALIGN ARCH_DMA_MINALIGN
+#else
+#define CONFIG_FEC_ALIG
On 03/13/2012 07:04 AM, Eric Nelson wrote:
ensure that transmit and receive buffers are cache-line aligned
invalidate cache for each packet as received
update receive buffer descriptors one cache line at a time
flush cache before transmitting
Original pa
On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote:
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
>
> +#if ARCH_DMA_MINALIGN > CONFIG_SYS_CACHELINE_SIZE
> +#define CONFIG_FEC_ALIGN ARCH_DMA_MINALIGN
> +#else
> +#define CONFIG_FEC_ALIGN CONFIG_SYS_CACHELINE_SIZE
> +#endif
i don't th
ensure that transmit and receive buffers are cache-line aligned
invalidate cache for each packet as received
update receive buffer descriptors one cache line at a time
flush cache before transmitting
Original patch by Marek:
http://lists.denx.de/pipe
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