Dear Mike Frysinger, > On Tuesday 13 March 2012 14:42:29 Eric Nelson wrote: > > On 03/13/2012 07:41 AM, Mike Frysinger wrote: > > > On Tuesday 13 March 2012 10:04:31 Eric Nelson wrote: > > >> --- a/drivers/net/fec_mxc.c > > >> +++ b/drivers/net/fec_mxc.c > > >> > > >> +#if ARCH_DMA_MINALIGN> CONFIG_SYS_CACHELINE_SIZE > > >> +#define CONFIG_FEC_ALIGN ARCH_DMA_MINALIGN > > >> +#else > > >> +#define CONFIG_FEC_ALIGN CONFIG_SYS_CACHELINE_SIZE > > >> +#endif > > > > > > i don't think this is something you should be checking. if this is an > > > actual problem (and i don't think it is), it's something we should > > > handle in common code. if you need to dma from memory, then use > > > ARCH_DMA_MINALIGN. > > > > Marek, you've mentioned some restrictions for other i.MX devices. > > > > Are you aware of any problem collapsing this? > > > > Note that other CPUs will need to have CONFIG_SYS_CACHELINE_SIZE to > > prevent the default of 64. > > and those cores should be making sure that ARCH_DMA_MINALIGN is sufficient > to handle those larger cache lines. this define provides two meanings: > minimum alignment for the DMA itself, and for sanely flushing the cache on > that dma buffer. so there should be no situation where ARCH_DMA_MINALIGN > is smaller than the cacheline size. > > the few boards i see defining CONFIG_SYS_CACHELINE_SIZE to 64 are all ARM > based, and ARM sets ARCH_DMA_MINALIGN to CONFIG_SYS_CACHELINE_SIZE if it's > defined > -mike
Eric, can you check also PPC /wrt to this? This driver is also used on PPC. Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
