On Tue, Nov 10, 2009 at 11:36:44AM -0600, Peter Tyser wrote:
> > Ok, here are my results, this is on a 8349EMDS-derived board. My
> > 8349EMDS eval board doesn't have ECC memory.
> >
> > 1) It might be nice to have something to print the current injection
> > registers. It is not a big deal, anyon
> Ok, here are my results, this is on a 8349EMDS-derived board. My
> 8349EMDS eval board doesn't have ECC memory.
>
> 1) It might be nice to have something to print the current injection
> registers. It is not a big deal, anyone using this should be an expert
> anyway.
Thanks for the feedback. I
On Mon, Nov 09, 2009 at 09:07:25PM -0600, Peter Tyser wrote:
[ big snip ]
> >
> > I haven't looked at your code. When I was running the old ecc command, I
> > had the 83xx reference manual open to decode the command's output, IIRC.
> >
> > PS - I'm happy to test stuff on 83xx, I'll try and find
Hi Ira,
On Mon, 2009-11-09 at 18:15 -0800, Ira W. Snyder wrote:
> On Mon, Nov 09, 2009 at 07:20:26PM -0600, Peter Tyser wrote:
> > On Tue, 2009-11-10 at 09:08 +0800, Liu Dave-R63238 wrote:
> > > > On Tue, 2009-11-10 at 08:42 +0800, Liu Dave-R63238 wrote:
> > > > > > IIRC, 85xx cache is enabled, so
On Mon, Nov 09, 2009 at 07:20:26PM -0600, Peter Tyser wrote:
> On Tue, 2009-11-10 at 09:08 +0800, Liu Dave-R63238 wrote:
> > > On Tue, 2009-11-10 at 08:42 +0800, Liu Dave-R63238 wrote:
> > > > > IIRC, 85xx cache is enabled, so when we do the ecc error inject
> > > > > test, What will happen before
On Tue, 2009-11-10 at 09:08 +0800, Liu Dave-R63238 wrote:
> > On Tue, 2009-11-10 at 08:42 +0800, Liu Dave-R63238 wrote:
> > > > IIRC, 85xx cache is enabled, so when we do the ecc error inject
> > > > test, What will happen before disable ecc error inject?
> > > > I-fetch may get wrong instruction?
> On Tue, 2009-11-10 at 08:42 +0800, Liu Dave-R63238 wrote:
> > > IIRC, 85xx cache is enabled, so when we do the ecc error inject
> > > test, What will happen before disable ecc error inject?
> > > I-fetch may get wrong instruction?
>
> If you're injecting multibit errors, yes, things could break
On Tue, 2009-11-10 at 08:42 +0800, Liu Dave-R63238 wrote:
> > IIRC, 85xx cache is enabled, so when we do the ecc error inject test,
> > What will happen before disable ecc error inject?
> > I-fetch may get wrong instruction?
If you're injecting multibit errors, yes, things could break down, much
l
> > IIRC, 85xx cache is enabled, so when we do the ecc error
> inject test,
> > What will happen before disable ecc error inject?
> > I-fetch may get wrong instruction?
>
> and
> Because cache is enabled, data bus assume 64 bits (it is normal case).
> The DDR bus will have 4-beat burst. So t
> IIRC, 85xx cache is enabled, so when we do the ecc error inject test,
> What will happen before disable ecc error inject?
> I-fetch may get wrong instruction?
and
Because cache is enabled, data bus assume 64 bits (it is normal case).
The DDR bus will have 4-beat burst. So the error informat
> You can inject data in the upper/lower 32 bit data path, or in the ecc
> path using the "ecc inject" command shown above. The inject command
> takes a mask that is XORed with the proper data, eg "ecc
> inject low 0x5"
> would result in data bits 0 and 2 always being swapped resulting in
> multi
On Tue, 2009-11-10 at 08:25 +0800, Liu Dave-R63238 wrote:
> How to use these command to test the ECC?
> Specially, how to inject multi error in 64bit data bus?
> > +U_BOOT_CMD(ecc, 5, 0, do_ecc,
> > + "support for DDR ECC features",
> > + "info - print ECC information\n"
> > +#if (CONFIG_NUM
7 AM
> To: u-boot@lists.denx.de
> Cc: Peter Tyser; Phillips Kim-R1AAHA; ga...@kernel.crashing.org
> Subject: [U-Boot] [PATCH 3/7] 83xx/85xx/86xx: Add ECC support
>
> Add a new 'ecc' command to interact with the 83xx, 85xx, and 86xx DDR
> ECC registers. The 'ecc'
Add a new 'ecc' command to interact with the 83xx, 85xx, and 86xx DDR
ECC registers. The 'ecc' command can inject data/ECC errors to simulate
errors and provides an 'info' subcommand which displays ECC error
information such as failure address, read vs expected data/ECC,
physical signal which fail
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