Hi Wolfgang,
On Wednesday 07 March 2012 05:35 PM, Wolfgang Denk wrote:
Dear Prabhakar Kushwaha,
In message<4f56deb0.6060...@freescale.com> you wrote:
+ _mas0 = MAS0_TLBSEL(1) |
+ MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB);
You are using an undocumented CONFIG_ option her
Dear Prabhakar Kushwaha,
In message <4f56deb0.6060...@freescale.com> you wrote:
>
> >> + _mas0 = MAS0_TLBSEL(1) |
> >> + MAS0_ESEL(CONFIG_DEBUGGER_TEMP_TLB);
> > You are using an undocumented CONFIG_ option here.
>
> This CONFIG_ is defined as part of documentation patch sent i
Hi Wolfgang,
On Tuesday 06 March 2012 08:15 PM, Wolfgang Denk wrote:
Dear Prabhakar Kushwaha,
In message<1329296055-28541-1-git-send-email-prabha...@freescale.com> you
wrote:
Update the NOR code base to support NOR-boot debugging.
It ovecome e500 and e500v2's second limitation i.e. IVPR + IV
Dear Prabhakar Kushwaha,
In message <1329296055-28541-1-git-send-email-prabha...@freescale.com> you
wrote:
> Update the NOR code base to support NOR-boot debugging.
> It ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be
> valid fetchable OP code address.
>
> While executin
Update the NOR code base to support NOR-boot debugging.
It ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be
valid fetchable OP code address.
While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared and the processor tr
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