On Mon, Jul 29, 2013 at 10:09 AM, Albert ARIBAUD
wrote:
> Hi Michael,
>
> On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang
> wrote:
>
>> Albert,
>>
>> That's not a correct characterization of the bug.
>>
>> The incoherent cache lines are from before the relocation stage. If
>> U-Boot is relocati
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If
U-Boot is relocating from RAM, and later copies the OS there without
invalidating those lines, then that's a bug in U-Boot.
Michael
On Mon, Jul 29, 2013 at 3:19 AM, Albe
Hi Michael,
On Mon, 29 Jul 2013 08:57:53 -0400, Michael Spang
wrote:
> Albert,
>
> That's not a correct characterization of the bug.
>
> The incoherent cache lines are from before the relocation stage. If
> U-Boot is relocating from RAM, and later copies the OS there without
> invalidating tho
(although this patch is more than two *years* old, it never got properly
answered to. I am doing so here to make sure future readers know why it
was not applied and won't be.)
Hi Michael,
On Thu, 17 Mar 2011 15:46:55 -0400, Michael Spang
wrote:
> If U-Boot is loaded from RAM and the OS is loade
Hi Michael,
Thanks, it is the key point:
"The problem is that it hits, but returns the wrong instructions."
Hi Aneesh,
Thanks for your sharing, it makes sense to check that way.
2011/3/21 Aneesh V :
> Hi Arden,
>
> On Sunday 20 March 2011 08:00 AM, arden jay wrote:
>>
>> Hi Michael,
>> Curiously,
Hi Arden,
On Sunday 20 March 2011 08:00 AM, arden jay wrote:
> Hi Michael,
> Curiously, have any idea how to test cache stuff?
Recently I did some cache testing. Here is the technique I used for
data-cache:
To test flush:
* Write a known pattern to a region of memory
* Flush the region
* Invalid
On 3/20/11, arden jay wrote:
> Hi Michael,
>
> I still have question. :)
>
> When ARM fetch instruction, it firstly try cache.
> It then should have cache miss, and forces to reload the instruction
> from memory?
>
> Why it will have problem while U-boot & Kernel at the same memory location?
If t
Hi Albert,
I got it, thanks your explaination.
2011/3/20 Albert ARIBAUD :
> Le 03/20/11 06:36, arden jay a écrit :
>>
>> Hi Michael,
>>
>> I still have question. :)
>>
>> When ARM fetch instruction, it firstly try cache.
>> It then should have cache miss, and forces to reload the instruction
>> f
Le 03/20/11 06:36, arden jay a écrit :
> Hi Michael,
>
> I still have question. :)
>
> When ARM fetch instruction, it firstly try cache.
> It then should have cache miss, and forces to reload the instruction
> from memory?
> Why it will have problem while U-boot& Kernel at the same memory location
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache.
It then should have cache miss, and forces to reload the instruction
from memory?
Why it will have problem while U-boot & Kernel at the same memory location?
2011/3/20 Michael Spang :
> On 3/19/11, arden jay
On 3/19/11, arden jay wrote:
> Hi Michael,
> Curiously, have any idea how to test cache stuff?
I don't have any good suggestions for testing cache stuff in general,
but this one is pretty easy to test if you have the board in question.
Because U-Boot is loaded *as if it were linux* by the manufac
Hi Michael,
Curiously, have any idea how to test cache stuff?
2011/3/18 Michael Spang :
> If U-Boot is loaded from RAM and the OS is loaded into an overlapping
> region, the instruction cache is not coherent when that OS is started.
> We must therefore invalidate the instruction cache in addition
If U-Boot is loaded from RAM and the OS is loaded into an overlapping
region, the instruction cache is not coherent when that OS is started.
We must therefore invalidate the instruction cache in addition to
cleaning the data cache.
Signed-off-by: Michael Spang
---
arch/arm/lib/cache.c |2 ++
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