Re: [U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Allow all supported prescaler values

2017-05-31 Thread Stefano Babic
On 03/05/2017 11:59, Benoît Thébaudeau wrote: > On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock > frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler > can divide by up to 512. Allow both of these settings. > > The maximum SD clock frequency in High Speed

Re: [U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Allow all supported prescaler values

2017-05-29 Thread Fabio Estevam
On Wed, May 3, 2017 at 6:59 AM, Benoît Thébaudeau wrote: > On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock > frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler > can divide by up to 512. Allow both of these settings. > > The maximum SD clock frequency in

[U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Allow all supported prescaler values

2017-05-03 Thread Benoît Thébaudeau
On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler can divide by up to 512. Allow both of these settings. The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25, this change makes it possible