On 03/05/2017 11:59, Benoît Thébaudeau wrote:
> On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
> frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
> can divide by up to 512. Allow both of these settings.
>
> The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
> this change makes it possible to get 48 MHz from the USB PLL
> (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
> (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
>
> Signed-off-by: Benoît Thébaudeau <ben...@wsystem.com>
> ---
> drivers/mmc/fsl_esdhc.c | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index f3c6358..ca72627 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -521,7 +521,13 @@ out:
>
> static void set_sysctl(struct mmc *mmc, uint clock)
> {
> - int div, pre_div;
> + int div = 1;
> +#ifdef ARCH_MXC
> + int pre_div = 1;
> +#else
> + int pre_div = 2;
> +#endif
> + int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
> struct fsl_esdhc_priv *priv = mmc->priv;
> struct fsl_esdhc *regs = priv->esdhc_regs;
> int sdhc_clk = priv->sdhc_clk;
> @@ -530,18 +536,13 @@ static void set_sysctl(struct mmc *mmc, uint clock)
> if (clock < mmc->cfg->f_min)
> clock = mmc->cfg->f_min;
>
> - if (sdhc_clk / 16 > clock) {
> - for (pre_div = 2; pre_div < 256; pre_div *= 2)
> - if ((sdhc_clk / pre_div) <= (clock * 16))
> - break;
> - } else
> - pre_div = 2;
> + while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
> + pre_div *= 2;
>
> - for (div = 1; div <= 16; div++)
> - if ((sdhc_clk / (div * pre_div)) <= clock)
> - break;
> + while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
> + div++;
>
> - pre_div >>= mmc->ddr_mode ? 2 : 1;
> + pre_div >>= 1;
> div -= 1;
>
> clk = (pre_div << 8) | (div << 4);
>
Applied to u-boot-imx -master, thanks !
Best regards,
Stefano Babic
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