Thierry,
On Mon, Jul 30, 2012 at 11:21 PM, Thierry Reding
wrote:
> In order for cache invalidation and flushing to work properly, the data
> and OOB buffers must be aligned to full cache lines.
>
> Signed-off-by: Thierry Reding
This patch, along with the Tegra: 'Enable NAND on TEC' patch, appli
On 07/31/2012 10:40 AM, Stephen Warren wrote:
> On 07/31/2012 12:21 AM, Thierry Reding wrote:
>> In order for cache invalidation and flushing to work properly, the data
>> and OOB buffers must be aligned to full cache lines.
>>
>> Signed-off-by: Thierry Reding
>
> You probably want to CC the NAND
On 07/31/2012 12:21 AM, Thierry Reding wrote:
> In order for cache invalidation and flushing to work properly, the data
> and OOB buffers must be aligned to full cache lines.
>
> Signed-off-by: Thierry Reding
You probably want to CC the NAND maintainer, Scott Wood (I have here) so
he can ack thi
+Scott
On Tue, Jul 31, 2012 at 7:21 AM, Thierry Reding
wrote:
> In order for cache invalidation and flushing to work properly, the data
> and OOB buffers must be aligned to full cache lines.
>
> Signed-off-by: Thierry Reding
Acked-by: Simon Glass
> ---
> common/cmd_nand.c | 4 ++--
> 1 file
In order for cache invalidation and flushing to work properly, the data
and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding
---
common/cmd_nand.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index a91
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