Re: [U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

2016-07-29 Thread Jagan Teki
On 25 July 2016 at 15:45, Vignesh R wrote: > By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as > QSPI fclk on dra7xx, it is possible to operate SPI slave clock at > 768.MHz which is the maximum supported frequency as per AM572x DM > SPRS953A. This helps to increase flash read

Re: [U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

2016-07-25 Thread Vignesh R
On Monday 25 July 2016 07:08 PM, Tom Rini wrote: > On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote: > >> By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as >> QSPI fclk on dra7xx, it is possible to operate SPI slave clock at >> 768.MHz which is the maximum supported

Re: [U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

2016-07-25 Thread Tom Rini
On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote: > By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as > QSPI fclk on dra7xx, it is possible to operate SPI slave clock at > 768.MHz which is the maximum supported frequency as per AM572x DM > SPRS953A. This helps to incr

[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

2016-07-25 Thread Vignesh R
By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as QSPI fclk on dra7xx, it is possible to operate SPI slave clock at 768.MHz which is the maximum supported frequency as per AM572x DM SPRS953A. This helps to increase flash read speed by ~2MB/s. Tested on DRA74 Rev G & H, DRA72