On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote: > By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as > QSPI fclk on dra7xx, it is possible to operate SPI slave clock at > 768.MHz which is the maximum supported frequency as per AM572x DM > SPRS953A. This helps to increase flash read speed by ~2MB/s. > > Tested on DRA74 Rev G & H, DRA72 Rev B & C EVMs.
And for the record, there is no HW that exists "in the wild" that would not support these options, yes? Thanks! -- Tom
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