Re: [U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

2017-09-25 Thread Jagan Teki
On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta wrote: > In some of the QSPI controller version, there must be atleast > 128bit data available in TX FIFO for any pop operation otherwise > error bit will be set. The code will not make any behavior change > for previous controller as the transfer data

Re: [U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

2017-09-13 Thread Suresh Gupta
Hi Jagan, > > > > -Original Message- > > From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > > Sent: Friday, August 11, 2017 4:44 PM > > To: Suresh Gupta > > Cc: u-boot@lists.denx.de; Jagan Teki ; > > york...@freescale.com; Anupam Kumar > > Subject: Re: [PATCH] spi: fsl_qspi: Copy 16

Re: [U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

2017-08-11 Thread Jagan Teki
On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta wrote: > In some of the QSPI controller version, there must be atleast > 128bit data available in TX FIFO for any pop operation otherwise > error bit will be set. The code will not make any behavior change > for previous controller as the transfer data

[U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

2017-06-05 Thread Suresh Gupta
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on