On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta <suresh.gu...@nxp.com> wrote: > In some of the QSPI controller version, there must be atleast > 128bit data available in TX FIFO for any pop operation otherwise > error bit will be set. The code will not make any behavior change > for previous controller as the transfer data size in ipcr register > is still the same. > > Patch is tested on LS1046A which do not require 16 bytes aligned and > LS1088A which require 16 bytes aligned data in TX FIFO > > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com> > Signed-off-by: Anupam Kumar <anupam.kuma...@nxp.com>
Applied to u-boot-spi//master thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
