Dear Ilya Yanok,
> On Tue, Jul 10, 2012 at 1:34 PM, Marek Vasut wrote:
> > > > aligned to
> > > > 16 bytes for arch with 16 byte cachelines.
> > >
> > > Yes, and this is exactly what we need.
> > >
> > > > ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); this stuff maybe? It'll be
> >
> > It isn't, E
On Tue, Jul 10, 2012 at 1:34 PM, Marek Vasut wrote:
> > > aligned to
> > > 16 bytes for arch with 16 byte cachelines.
> >
> > Yes, and this is exactly what we need.
>
> > > ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); this stuff maybe? It'll be
> It isn't, EHCI needs it aligned on 32 byte boundary.
Dear Ilya Yanok,
> Hi Marek,
>
> On Tue, Jul 10, 2012 at 6:17 AM, Marek Vasut wrote:
> > > Well, of course we need proper alignment for cache stuff (well,
> > > actually
> >
> > we
> >
> > > can skip this alignment thing for the buffer we will flush as long as
> > > all buffers we are going to
Hi Marek,
On Tue, Jul 10, 2012 at 6:17 AM, Marek Vasut wrote:
> > Well, of course we need proper alignment for cache stuff (well, actually
> we
> > can skip this alignment thing for the buffer we will flush as long as all
> > buffers we are going to invalidate are properly aligned/sized... but
>
Dear Ilya Yanok,
> Dear Marek,
>
> On Mon, Jul 9, 2012 at 4:45 AM, Marek Vasut wrote:
> > > But in practice it works without any alignment... ok, you made me read
> >
> > the
> >
> > > spec ;)
> > > page 55: "For the page 0 current offset interpretation, this field is
> > > the byte offset int
Dear Marek,
On Mon, Jul 9, 2012 at 4:45 AM, Marek Vasut wrote:
>
> > But in practice it works without any alignment... ok, you made me read
> the
> > spec ;)
> > page 55: "For the page 0 current offset interpretation, this field is the
> > byte offset into the current page"
>
>
> See the thread
Dear Ilya Yanok,
> Dear Marek,
>
> On Mon, Jul 9, 2012 at 1:31 AM, Marek Vasut wrote:
> > > non-ARMv7 system now to do some testing...
> > > But it used to work without any alignment, right? (with disabled
> > > dcache,
> >
> > of
> >
> > > course)
> > > That makes me think that data buffers d
Dear Marek,
On Mon, Jul 9, 2012 at 1:31 AM, Marek Vasut wrote:
> > non-ARMv7 system now to do some testing...
> > But it used to work without any alignment, right? (with disabled dcache,
> of
> > course)
> > That makes me think that data buffers don't need any alignment (from USB
> > pov, not ca
Dear Ilya Yanok,
> Dear Marek,
>
> On Sun, Jul 8, 2012 at 10:59 PM, Marek Vasut wrote:
> > btw. this will fail with cache line < 32 .
>
> Hm.. I have to admit I'm not very much into USB specs and I don't have any
> non-ARMv7 system now to do some testing...
> But it used to work without any ali
Dear Marek,
On Sun, Jul 8, 2012 at 10:59 PM, Marek Vasut wrote:
> btw. this will fail with cache line < 32 .
>
Hm.. I have to admit I'm not very much into USB specs and I don't have any
non-ARMv7 system now to do some testing...
But it used to work without any alignment, right? (with disabled d
Dear Ilya Yanok,
> Align buffers passed to the USB code to cache line size so
> they can be DMAed safely.
>
> Signed-off-by: Ilya Yanok
> ---
> Depens on Marek's patch [1] for DEFINE_CACHE_ALIGN_BUFFER.
Isn't it your patch anyway? You should get the credit for that series, you know
...
btw. t
Align buffers passed to the USB code to cache line size so
they can be DMAed safely.
Signed-off-by: Ilya Yanok
---
Depens on Marek's patch [1] for DEFINE_CACHE_ALIGN_BUFFER.
[1] http://patchwork.ozlabs.org/patch/169619/
drivers/usb/eth/smsc95xx.c | 13 +
1 file changed, 9 inserti
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