On Tue, Jul 10, 2012 at 1:34 PM, Marek Vasut <marek.va...@gmail.com> wrote:
> > > aligned to > > > 16 bytes for arch with 16 byte cachelines. > > > > Yes, and this is exactly what we need. > > > > ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); this stuff maybe? It'll be > It isn't, EHCI needs it aligned on 32 byte boundary. > > It doesn't. I posted the page number with data buffer description in EHCI spec upper in this thread. There is no alignment requirement at all. Controller is fine with any address. _We_ need the buffer to be cache line aligned to perform cache operations safely. Regards, Ilya.
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