On Mar 6, 2011, at 10:17 PM, Kumar Gala wrote:
> From: Haiying Wang
>
> P1021 has some QE pins which need to be set in pmuxcr register before
> using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
> UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
> b
From: Haiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LB
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