Otavio,
On Mon, Apr 28, 2014 at 11:53 PM, Fabio Estevam wrote:
>> So use 18?
>
> It would also break the existing IOMUX config layout.
>
> Bit 63 is free, so I came up with this change:
Please discard this one.
Actually I have a better proposal now and will submit the new patch
for you to try
On Mon, Apr 28, 2014 at 9:27 PM, Otavio Salvador
wrote:
> On Mon, Apr 28, 2014 at 9:14 PM, Fabio Estevam wrote:
>> On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador
>> wrote:
#define PAD_CTL_HYS(1 << 16)
+#define PAD_CTL_LVE(1 << 17)
+#define PAD_CTL_LVE_BI
On Mon, Apr 28, 2014 at 9:14 PM, Fabio Estevam wrote:
> On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador
> wrote:
>>> #define PAD_CTL_HYS(1 << 16)
>>> +#define PAD_CTL_LVE(1 << 17)
>>> +#define PAD_CTL_LVE_BIT(1 << 22)
>>
>> This conflicts with:
>>
>> #def
On Mon, Apr 28, 2014 at 8:40 PM, Otavio Salvador
wrote:
>> #define PAD_CTL_HYS(1 << 16)
>> +#define PAD_CTL_LVE(1 << 17)
>> +#define PAD_CTL_LVE_BIT(1 << 22)
>
> This conflicts with:
>
> #define NO_PAD_CTRL (1 << 17)
Correct, I missed the NO_PAD_CTRL defin
On Mon, Apr 28, 2014 at 8:11 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> On mx6sl there is a LVE (Low Voltage Enable) in the IOMUXC_SW_PAD_CTL
> register.
>
> LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
> calculation easier we can define it as bit 17 as this bit
From: Fabio Estevam
On mx6sl there is a LVE (Low Voltage Enable) in the IOMUXC_SW_PAD_CTL register.
LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as bit 17 as this bit is unused and fits the
current MUX_PAD_CTRL_MASK mask.
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