On 03/26/2015 10:24 PM, Minghuan Lian wrote:
> Freescale PCIe controllers v3.0 and later need to set bit
> CFG_READY to allow all inbound configuration transactions
> to be processed normally when in EP mode. However, bit
> CFG_READY has been moved from PCIe configuration space to
> CCSR PCIe con
Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch
2 matches
Mail list logo