Hi Fabio and Hector,
On 12/04/2015 10:43 AM, Eric Nelson wrote:
> On 12/04/2015 10:38 AM, Eric Nelson wrote:
>> On 12/04/2015 10:32 AM, Eric Nelson wrote:
>>> The low four bits of the SYSCTL register are reserved on the USDHC
>>> controller on i.MX6 and i.MX7 processors, but are used for clocking
The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.
Guard against their usage by hiding the bit mask macros on those
processors.
These bits are used to prevent glitches when changing c
Thanks Hector,
On 12/04/2015 11:51 AM, Hector Palacios wrote:
> On 12/04/2015 07:33 PM, Eric Nelson wrote:
>> On 12/04/2015 10:43 AM, Eric Nelson wrote:
...
>> From what I can tell, the linux kernel doesn't do this test and
>> doesn't appear to have any trouble.
>>
>> What code base are you runni
Thanks Hector,
On 12/04/2015 11:39 AM, Hector Palacios wrote:
> Hi,
>
> On 12/04/2015 06:32 PM, Eric Nelson wrote:
>> The low four bits of the SYSCTL register are reserved on the USDHC
>> controller on i.MX6 and i.MX7 processors, but are used for clocking
>> operations on earlier models.
>>
>> Gu
Hi Eric,
On 12/04/2015 07:33 PM, Eric Nelson wrote:
> Hi Fabio and Hector,
>
> On 12/04/2015 10:43 AM, Eric Nelson wrote:
>> On 12/04/2015 10:38 AM, Eric Nelson wrote:
>>> On 12/04/2015 10:32 AM, Eric Nelson wrote:
The low four bits of the SYSCTL register are reserved on the USDHC
contr
Hi,
On 12/04/2015 06:32 PM, Eric Nelson wrote:
> The low four bits of the SYSCTL register are reserved on the USDHC
> controller on i.MX6 and i.MX7 processors, but are used for clocking
> operations on earlier models.
>
> Guard against their usage by hiding the bit mask macros on those
> processo
Hi Eric,
On 12/04/2015 06:43 PM, Eric Nelson wrote:
> On 12/04/2015 10:38 AM, Eric Nelson wrote:
>> On 12/04/2015 10:32 AM, Eric Nelson wrote:
>>> The low four bits of the SYSCTL register are reserved on the USDHC
>>> controller on i.MX6 and i.MX7 processors, but are used for clocking
>>> operatio
On Fri, Dec 4, 2015 at 3:43 PM, Eric Nelson wrote:
> Fabio, I haven't been able to reproduce the "mmc erase/ENGcm03648"
> issue (with or without a code change) for a couple of hours now.
>
> Can you give this a spin?
Sure, just gave it a try and the 'mmc erase' issue still happens.
I think your
Hi Michael,
On 12/04/2015 10:40 AM, Michael Trimarchi wrote:
> On Fri, Dec 4, 2015 at 6:32 PM, Eric Nelson wrote:
...
>> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
>> index c5054d6..1ccc576 100644
>> --- a/drivers/mmc/fsl_esdhc.c
>> +++ b/drivers/mmc/fsl_esdhc.c
>> @@ -502,15
Hi
On Fri, Dec 4, 2015 at 6:49 PM, Eric Nelson wrote:
> Hi Michael,
>
> On 12/04/2015 10:40 AM, Michael Trimarchi wrote:
>> On Fri, Dec 4, 2015 at 6:32 PM, Eric Nelson wrote:
> ...
>
>>> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
>>> index c5054d6..1ccc576 100644
>>> --- a/dr
On 12/04/2015 10:38 AM, Eric Nelson wrote:
> On 12/04/2015 10:32 AM, Eric Nelson wrote:
>> The low four bits of the SYSCTL register are reserved on the USDHC
>> controller on i.MX6 and i.MX7 processors, but are used for clocking
>> operations on earlier models.
>>
>> Guard against their usage by hi
Hi
On Fri, Dec 4, 2015 at 6:32 PM, Eric Nelson wrote:
> The low four bits of the SYSCTL register are reserved on the USDHC
> controller on i.MX6 and i.MX7 processors, but are used for clocking
> operations on earlier models.
>
> Guard against their usage by hiding the bit mask macros on those
> p
On 12/04/2015 10:32 AM, Eric Nelson wrote:
> The low four bits of the SYSCTL register are reserved on the USDHC
> controller on i.MX6 and i.MX7 processors, but are used for clocking
> operations on earlier models.
>
> Guard against their usage by hiding the bit mask macros on those
> processors.
>
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