Hi,
> From: Patrick DELAUNAY
> Sent: mardi 28 janvier 2020 10:11
>
> From: Antonio Borneo
>
> LTDC modifies the clock frequency to adapt it to the display. Such frequency
> change is not detected by the FDCAN driver that instead cache the value at
> probe
> and pretend to use it later.
>
> K
On 1/28/20 10:11 AM, Patrick Delaunay wrote:
> From: Antonio Borneo
>
> LTDC modifies the clock frequency to adapt it to the display. Such
> frequency change is not detected by the FDCAN driver that instead
> cache the value at probe and pretend to use it later.
>
> Keep the LTDC alone on PLL4_Q
On 2/6/20 9:59 AM, Patrick DELAUNAY wrote:
> Hi Marek,
Hello Patrick
[...]
>> My problem is with the bootloader-Linux clock tree dependency. That
>> dependency
>> should not exist or be minimized, otherwise you end up with a very poor
>> long-term
>> experience, see above. And if you want for
Hi Marek,
> From: Marek Vasut
> Sent: mercredi 5 février 2020 03:23
>
> On 2/4/20 2:16 PM, Patrick DELAUNAY wrote:
> > Hi Marek
>
> Hello Patrick,
>
> [...]
>
> What I think you are missing is that not everyone will update
> ATF/U-Boot/Linux in lockstep. That is the problem you need
On 2/4/20 2:16 PM, Patrick DELAUNAY wrote:
> Hi Marek
Hello Patrick,
[...]
What I think you are missing is that not everyone will update
ATF/U-Boot/Linux in lockstep. That is the problem you need to deal with
here.
>>>
>>> I understood the possible issue and I hope that I will be
Hi Marek
> From: Marek Vasut
> Sent: dimanche 2 février 2020 18:28
>
> On 1/31/20 9:15 AM, Patrick DELAUNAY wrote:
> > Hi Marek,
>
> Hi,
>
> >> From: Marek Vasut
> >> Sent: jeudi 30 janvier 2020 03:23
> >>
> >> On 1/29/20 5:51 PM, Patrick DELAUNAY wrote:
> >>> Hi Marek,
> >>
> >> Hi,
> >>
> >
On 1/31/20 9:15 AM, Patrick DELAUNAY wrote:
> Hi Marek,
Hi,
>> From: Marek Vasut
>> Sent: jeudi 30 janvier 2020 03:23
>>
>> On 1/29/20 5:51 PM, Patrick DELAUNAY wrote:
>>> Hi Marek,
>>
>> Hi,
>>
From: Marek Vasut
Sent: mardi 28 janvier 2020 13:16
On 1/28/20 10:11 AM, Patrick
Hi Marek,
> From: Marek Vasut
> Sent: jeudi 30 janvier 2020 03:23
>
> On 1/29/20 5:51 PM, Patrick DELAUNAY wrote:
> > Hi Marek,
>
> Hi,
>
> >> From: Marek Vasut
> >> Sent: mardi 28 janvier 2020 13:16
> >>
> >> On 1/28/20 10:11 AM, Patrick Delaunay wrote:
> >>> From: Antonio Borneo
> >>>
> >>
On 1/29/20 5:51 PM, Patrick DELAUNAY wrote:
> Hi Marek,
Hi,
>> From: Marek Vasut
>> Sent: mardi 28 janvier 2020 13:16
>>
>> On 1/28/20 10:11 AM, Patrick Delaunay wrote:
>>> From: Antonio Borneo
>>>
>>> LTDC modifies the clock frequency to adapt it to the display. Such
>>> frequency change is no
Hi Marek,
> From: Marek Vasut
> Sent: mardi 28 janvier 2020 13:16
>
> On 1/28/20 10:11 AM, Patrick Delaunay wrote:
> > From: Antonio Borneo
> >
> > LTDC modifies the clock frequency to adapt it to the display. Such
> > frequency change is not detected by the FDCAN driver that instead
> > cache
On 1/28/20 10:11 AM, Patrick Delaunay wrote:
> From: Antonio Borneo
>
> LTDC modifies the clock frequency to adapt it to the display. Such
> frequency change is not detected by the FDCAN driver that instead
> cache the value at probe and pretend to use it later.
>
> Keep the LTDC alone on PLL4_Q
From: Antonio Borneo
LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
cache the value at probe and pretend to use it later.
Keep the LTDC alone on PLL4_Q by moving the FDCAN to PLL4_R.
Signed-off-by: Antonio Bor
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