On 2/27/24 09:57, Lukas Funke wrote:
On 27.02.2024 09:45, Michal Simek wrote:
On 2/27/24 09:40, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
Some zynqmp SoCs (the cg series) only have two cpus. Thus, for some
cases the cpu-affinity has to adapted, because cpu3 and cpu4 are
On 27.02.2024 09:45, Michal Simek wrote:
On 2/27/24 09:40, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
Some zynqmp SoCs (the cg series) only have two cpus. Thus, for some
cases the cpu-affinity has to adapted, because cpu3 and cpu4 are
interrupt-affinity right?
Duh. Can you
On 2/27/24 09:40, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
Some zynqmp SoCs (the cg series) only have two cpus. Thus, for some
cases the cpu-affinity has to adapted, because cpu3 and cpu4 are
interrupt-affinity right?
missing. By adding a label to the pmu fwnode the cpu
From: Lukas Funke
Some zynqmp SoCs (the cg series) only have two cpus. Thus, for some
cases the cpu-affinity has to adapted, because cpu3 and cpu4 are
missing. By adding a label to the pmu fwnode the cpu affinity can
be adapted in a device specific dt.
Signed-off-by: Lukas Funke
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arch/arm/d
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