[PATCH] MAINTAINERS, git-mailrc: socfpga: Update email to Altera

From: Tien Fong Chee Altera officially split off from Intel, the email need be updated to ensure uninterrupted support and communication Signed-off-by: Tien Fong Chee --- doc/git-mailrc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/git-mailrc b/doc/git-mailrc index

[PATCH v1 20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS

From: Alif Zakuan Yuslaimi Add the required configuration in the U-Boot env to enable Linux QSPI boot with UBI / UBIFS. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + include/configs/socfpga_soc64_common.h | 5 + 2

[PATCH v1 19/20] arm: socfpga: soc64: Add support for board_boot_order()

From: Tien Fong Chee Add board_boot_order() to retrieve the list of boot devices from spl-boot-order property in device tree. This board_boot_order() would be used for all Intel SOC64 devices. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/spl_soc64.c | 103

[PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC

From: Tien Fong Chee Enable XGMAC for SoCFPGA Agilex5 devkit. Signed-off-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 81bbe967dcf..a4a5064d9c2 100644

[PATCH v1 17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA

From: Tien Fong Chee Add SPL support for Agilex5 SoCFPGA. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile | 3 ++ arch/arm/mach-socfpga/spl_agilex5.c | 84 + 2 files changed, 87 insertions(+) create mode 100644 arch/arm/mach-socfpga

[PATCH v1 16/20] ddr: altera: Add DDR driver for Agilex5 series

/sdram_agilex5.c diff --git a/MAINTAINERS b/MAINTAINERS index 2050ae24df8..1837d283b2f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -146,8 +146,10 @@ ARM ALTERA SOCFPGA M: Marek Vasut M: Simon Goldschmidt M: Tien Fong Chee +M: Tingting Meng S: Maintained T: git

[PATCH v1 13/20] arm: socfpga: Export board ID as U-Boot environment variable

From: Tien Fong Chee Board ID is exported as environment variable for use to boot Linux with FIT configuration. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc_soc64.c| 5 + 2 files changed, 6 insertions(+) diff --git

[PATCH v1 14/20] configs: agilex5: Add configuration for malloc pool

From: Tien Fong Chee Adding configuration for SPL malloc pool. Signed-off-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index dc1cef3754e..81bbe967dcf

[PATCH v1 15/20] arm: socfpga: smc: Add memory coherency support to mailbox command

From: Tien Fong Chee As cache is enabled in U-Boot and disabled in ATF(BL31). We need to perform cache flush of buffers that are shared between U-Boot and ATF using secure monitor calls. Signed-off-by: Mahesh Rao Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/smc_api.c | 13

[PATCH v1 12/20] arm: socfpga: agilex5: Update CPU info

From: Tien Fong Chee Update the print info per Agilex 5. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc_soc64.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index a6cc78454da

[PATCH v1 06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings

From: Tien Fong Chee These configuration settings are required to enable cache maintenance and access between initiators and targets. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 209 +++ 1 file changed, 209 insertions(+) diff --git a/arch

[PATCH v1 10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU

From: Tien Fong Chee set/way instructions "dc cisw" ehich is used by the "dcache flush" command only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in cache coherency unit, hence this patch enables data flush from system memory cache of CCU into

[PATCH v1 11/20] arm: socfpga: agilex5: Add SMMU initialization

From: Tien Fong Chee Allow non-secure accesses only with SMMU peripherals. This would protect the content in DDR secure region from accidentally modified by SMMU peripherals. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 34 arch/arm

[PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device

From: Tien Fong Chee The reset driver can support both cold reset and warm reset with SMCC to ATF. Signed-off-by: Tien Fong Chee --- arch/arm/Kconfig| 1 + drivers/sysreset/Kconfig| 7 +++ drivers/sysreset/Makefile | 1

[PATCH v1 08/20] arm: dts: agilex5: Enable XGMAC

From: Tien Fong Chee Enable XGMAC for SoCFPGA Agilex5 devkit. Signed-off-by: Tien Fong Chee --- .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33 +++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts

[PATCH v1 07/20] arm: dts: agilex5: Add firewall configure settings

From: Tien Fong Chee These firewall configure settings are needed to disable firewall on respective hardware component so both secure and non-secure transactions are allowed. Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 166 +++ 1 file

[PATCH v1 05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device

From: Tien Fong Chee Agilex5 supports both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and Agilex5 device. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach

[PATCH v1 04/20] arm: socfpga: agilex5: Add low level initialization

From: Tien Fong Chee Create new low level initialization for Agile5 due to the new ARM core composition and warm reset behavior. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/Makefile| 1 + .../include/mach/reset_manager_soc64.h| 12 +++- arch/arm/mach

[PATCH v1 03/20] linker: Add SPL linker script for SoC64 devices

From: Tien Fong Chee Add a new .data section for preserving the original state of the .data section of SoC64 SPL. This new .data section is required to make SPL reentrant after warm reset. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 80

[PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock manager

From: Tien Fong Chee Adding mechanism to retrieve base address for Agilex5 Clock Mananger. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc.c | 24 ++-- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach

[PATCH v1 01/20] arm: socfpga: agilex5: Add new system manager base addresses

From: Tien Fong Chee Initial creation of new system manager base addresses for Agilex5. Signed-off-by: Tien Fong Chee --- .../include/mach/system_manager_soc64.h | 129 +++--- 1 file changed, 83 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach

[PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot

From: Tien Fong Chee This patch set introduces boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The changes include: 1. Board-specific configurations and setup required to enable Agilex 5 operation in U-Boot. 2. Integration of cache coherency unit (CCU

[PATCH] intel: n5x: ddr: update license

From: Tien Fong Chee All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_n5x.c | 4 ++-- 1 file changed, 2

[PATCH] ddr: altera: Stratix10: Use phys_size_t for memory size

From: Tien Fong Chee Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_s10.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions

[PATCH] ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS

From: Tien Fong Chee Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.h | 2 +- 1 file

[PATCH] mtd: spi-nor-ids: add Macronix flash entry

From: Tien Fong Chee Add Macronix mx25u51245g flash entry, so this can be used on SoCFPGA devices. Signed-off-by: Tien Fong Chee --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index

[PATCH] ddr: socfpga: Fix integer overflow that caused DDR size mismatched

From: Tien Fong Chee Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/

[PATCH] ddr: socfpga: stratix10: Use phys_size_t for memory size

From: Tien Fong Chee Replace with phys_size_t for better scalable. phys_size_t is defined in arch/arm/include/asm/types.h . Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_s10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_s10.c b

[U-Boot] [PATCH 2/2] drivers: ubi: Adding UBI loader for SPI flash

From: Tien Fong Chee Adding UBI support for SPI flash. Signed-off-by: Tien Fong Chee --- common/spl/spl_ubi.c| 11 ++- drivers/mtd/spi/sf-uclass.c | 30 ++ include/spi_flash.h | 10 ++ 3 files changed, 50 insertions(+), 1 deletion

[U-Boot] [PATCH 1/2] mtd: spi: Add SYS_SPI_BLOCK_SIZE to Kconfig

From: Tien Fong Chee Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access

[U-Boot] [PATCH] Arm: dts: socfpga: Remove invalid property from chose node

From: Tien Fong Chee Finding bitstream from cff-file is no longer valid after bitstream is built into FIT image and loaded by generic firmware loader. Remove cff-file as this is legacy implementation from A10 downstream. Signed-off-by: Tien Fong Chee --- arch/arm/dts

[U-Boot] [PATCH] reset: socfpga: release more A10 peripherals out of reset

From: Tien Fong Chee Current implementation almost release all peripherals out of reset for gen5, but A10 has more peripherals than gen5, hence this patch is required to release the rest of peripherals to support old kernels. Signed-off-by: Tien Fong Chee --- drivers/reset/reset-socfpga.c | 3

[U-Boot] [PATCH v13 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v13 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v13 - No

[U-Boot] [PATCH v13 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL . The result of calculation is come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000). Signed-off-by: Tien Fong Chee --- Previous records of discussion

[U-Boot] [PATCH v13 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v13 - No changes. changes for v12 - No changes. changes for v11 - No changes. changes for v10 - No changes. changes for

[U-Boot] [PATCH v13 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling

From: Tien Fong Chee Current watchdog reset is misplaced after for-loop status polling, so this poses a risk that watchdog can't be reset timely if polling taking longer than watchdog timeout. This patch moving the watchdog reset into polling to ensure the watchdog can be reset timely. S

[U-Boot] [PATCH v13 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v13 - No changes. changes for v12 - No changes. changes for v11 - Replaced core image node "-2" with "-1", the numeric associates the co

[U-Boot] [PATCH v13 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v13 - No changes

[U-Boot] [PATCH v13 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver

From: Tien Fong Chee Ensure all the debug messages are always prefix with "FPGA: " and comment beginning with uppercase letter. Signed-off-by: Tien Fong Chee --- changes for v13 - No changes. changes for v12 - Improved the commit messages. changes for v11 - No changes. chang

[U-Boot] [PATCH v13 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v13 - No changes. changes for v12 - No changes. changes for v11 - No changes. changes for v10 - No changes

[U-Boot] [PATCH v13 0/9] Add support for loading FPGA bitstream

From: Tien Fong Chee This version mainly resolved comments from Simon in [v12]. This series is working on top of u-boot.git http://git.denx.de/u-boot.git [v12]: https://patchwork.ozlabs.org/cover/1058282/ [v11]: https://www.mail-archive.com/u-boot@lists.denx.de/msg318174.html [v10]: https

[U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v12 - No changes. changes for v11 - No changes. changes for v10 - No changes. changes for v9 - No changes. changes for

[U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v12 - No

[U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL . The result of calculation is come from after applying some few patches which are required for optimizing vfat and maximizing resusable of the memory pool, and then followed by the size required

[U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v12 - No changes

[U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v12 - No changes. changes for v11 - Replaced core image node "-2" with "-1", the numeric associates the core and periph images in ca

[U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver

From: Tien Fong Chee Ensure all the debug messages are always prefix with "FPGA: " and comment beginning with uppercase letter. Signed-off-by: Tien Fong Chee --- changes for v12 - Improved the commit messages. changes for v11 - No changes. changes for v10 - This patch was spli

[U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling

From: Tien Fong Chee Ensure the watchdog is reset timely on each status polling. Signed-off-by: Tien Fong Chee --- changes for v12 - Improved the commit messages. changes for v11 - No changes. changes for v10 - This patch was split out from [PATCH v10 5/9] ARM: socfpga: Add FPGA drivers

[U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v12 - No changes. changes for v11 - No changes. changes for v10 - No changes. changes for v9 - No changes

[U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream

From: Tien Fong Chee This version mainly resolved comments from Dinh in [v11]. This series is working on top of u-boot.git http://git.denx.de/u-boot.git These patches are required before applying this series of patches 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block device

[U-Boot] [PATCH v11 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v11 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep

[U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee After some series of patches to maximise reusable of memory pool, here come to result of reasonable size required for whole SDMMC boot working on A10 SoCDK. Size required come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000

[U-Boot] [PATCH v11 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v10

[U-Boot] [PATCH v11 3/9] ARM: socfpga: Cleaning up the messages

From: Tien Fong Chee Ensure the comment and debug messages are always consistent with the rest. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga_arria10.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga

[U-Boot] [PATCH v11 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v8 - Added FIT related

[U-Boot] [PATCH v11 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v11 - Replaced core image node "-2" with "-1", the numeric associates the core and periph images in case where there are multip

[U-Boot] [PATCH v11 4/9] ARM: socfpga: Move the watchdog reset to the looping location

From: Tien Fong Chee Ensure the watchdog is reset timely if the looping is long. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga_arria10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index

[U-Boot] [PATCH v11 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v8 - Removed explanation about support for altr,bitstream-core changes for v7 - Provided example of setting

[U-Boot] [PATCH v11 0/9] Add support for loading FPGA bitstream

From: Tien Fong Chee This version mainly assign "-1" to both periph and core images in patch[2/9] because the numeric associates the core and periph images in cases where there are multiple. This series is working on top of u-boot.git http://git.denx.de/u-boot.git These patches ar

[U-Boot] [PATCH v10 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v10 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep

[U-Boot] [PATCH v10 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v10

[U-Boot] [PATCH v10 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee After some series of patches to maximise reusable of memory pool, here come to result of reasonable size required for whole SDMMC boot working on A10 SoCDK. Size required come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000

[U-Boot] [PATCH v10 4/9] ARM: socfpga: Move the watchdog reset to the looping location

From: Tien Fong Chee Ensure the watchdog is reset timely if the looping is long. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga_arria10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index

[U-Boot] [PATCH v10 3/9] ARM: socfpga: Cleaning up the messages

From: Tien Fong Chee Ensure the comment and debug messages are always consistent with the rest. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga_arria10.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga

[U-Boot] [PATCH v10 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v8 - Added FIT related

[U-Boot] [PATCH v10 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v10 - Replaced both periph anc core image nodes "@1" and "@2" with "-1", the numeric associates the core and periph images in c

[U-Boot] [PATCH v10 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v8 - Removed explanation about support for altr,bitstream-core changes for v7 - Provided example of setting

[U-Boot] [PATCH v10 0/9] Add support for loading FPGA bitstream

From: Tien Fong Chee This version mainly resolved some comments from Simek in [v9]. This series is working on top of u-boot.git http://git.denx.de/u-boot.git These patches are required before applying this series of patches 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block

[U-Boot] [PATCH v2] misc: fs_loader: Replace label with DT phandle

From: Tien Fong Chee In previously label which will be expanded to the node's full path was used, and now replacing label with most commonly used DT phandle. The codes were changed accordingly to the use of DT phandle and supporting multiple instances. Signed-off-by: Tien Fong

[U-Boot] [PATCH v10 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee After some series of patches to maximise reusable of memory pool, here come to result of reasonable size required for whole SDMMC boot working on A10 SoCDK. Size required come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000

[U-Boot] [PATCH v10 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v10

[U-Boot] [PATCH v10 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v10 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v10 - Replaced both image nodes "@1" and "@2" with "-1" and "-2" respectively. changes for v9 - Reordered the images and

[U-Boot] [PATCH v10 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep

[U-Boot] [PATCH v10 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v8 - Added FIT related

[U-Boot] [PATCH v10 4/9] ARM: socfpga: Move the watchdog reset to the looping location

From: Tien Fong Chee Ensure the watchdog is reset timely if the looping is long. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga_arria10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index

[U-Boot] [PATCH v10 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v8 - Removed explanation about support for altr,bitstream-core changes for v7 - Provided example of setting

[U-Boot] [PATCH v10 3/9] ARM: socfpga: Cleaning up the messages

From: Tien Fong Chee Ensure the comment and debug messages are always consistent with the rest. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga_arria10.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga

[U-Boot] [PATCH v10 0/9] Add support for loading FPGA bitstream

From: Tien Fong Chee This version mainly resolved some comments from Simek in [v9]. This series is working on top of u-boot.git http://git.denx.de/u-boot.git These patches are required before applying this series of patches 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block

[U-Boot] [PATCH v9 6/7] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep

[U-Boot] [PATCH v9 5/7] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v9 - Used

[U-Boot] [PATCH v9 7/7] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee After some series of patches to maximise reusable of memory pool, here come to result of reasonable size required for whole SDMMC boot working on A10 SoCDK. Size required come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000

[U-Boot] [PATCH v9 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v9 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v8 - Added FIT related

[U-Boot] [PATCH v9 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v8 - Reordered the images and fpga configurations. - Removed the load property at core image. changes for v8 - Changed the FPGA node name to fpga-core and fpga

[U-Boot] [PATCH v9 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v8 - Removed explanation about support for altr,bitstream-core changes for v7 - Provided example of setting

[U-Boot] [PATCH v9 0/7] Add support for loading FPGA bitstream

From: Tien Fong Chee This version mainly resolved comments from Marek in [v8]. This series is working on top of u-boot.git - http://git.denx.de/u-boot.git . These patches are required before applying this series of patches 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block

[U-Boot] [PATCH] fpga: Replace char * with const char * for filename

From: Tien Fong Chee Ensure the string for filename is always constant, otherwise it can be corrupted by the writing. Signed-off-by: Tien Fong Chee --- drivers/fpga/zynqpl.c |3 ++- include/fpga.h|2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers

[U-Boot] [PATCH] misc: fs_loader: Replace label with DT phandle

From: Tien Fong Chee In previously label which will be expanded to the node's full path was used, and now replacing label with most commonly used DT phandle. The codes were changed accordingly to the use of DT phandle and supporting multiple instances. Signed-off-by: Tien Fong Chee ---

[U-Boot] [PATCH v8 5/8] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v8 - Added FIT related

[U-Boot] [PATCH v8 8/8] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

From: Tien Fong Chee After some series of patches to maximise reusable of memory pool, here come to result of reasonable size required for whole SDMMC boot working on A10 SoCDK. Size required come from default max cluster(0x1) + others(0x2000) + additional memory for headroom(0x3000

[U-Boot] [PATCH v8 6/8] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs

From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v7

[U-Boot] [PATCH v8 7/8] ARM: socfpga: Synchronize the configuration for A10 SoCDK

From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep

[U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading

From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA

[U-Boot] [PATCH v8 3/8] fit: Add function declarations to the header file

From: Tien Fong Chee Adding some function declarations to the header file, so these functions can be referred by other C files. Signed-off-by: Tien Fong Chee --- include/image.h | 4 1 file changed, 4 insertions(+) diff --git a/include/image.h b/include/image.h index 83a2d41..f839443

[U-Boot] [PATCH v8 1/8] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v8 - Removed explanation about support for altr,bitstream-core changes for v7 - Provided example of setting

  1   2   3   4   5   >