From: Tien Fong Chee <tien.fong.c...@intel.com>
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <mahesh....@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
---
arch/arm/mach-socfpga/smc_api.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
index ebaa0b8fa17..dac888c399f 100644
--- a/arch/arm/mach-socfpga/smc_api.c
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
*
*/
+#include <cpu_func.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <linux/errno.h>
@@ -40,10 +41,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent,
u32 *resp_buf_len,
args[2] = len;
args[3] = urgent;
args[4] = (u64)resp_buf;
- if (resp_buf_len)
+
+ if (arg && len > 0)
+ flush_dcache_range((u64)arg, (u64)arg + len);
+
+ if (resp_buf && resp_buf_len && *resp_buf_len > 0) {
args[5] = *resp_buf_len;
- else
+ flush_dcache_range((u64)resp_buf, (u64)resp_buf +
*resp_buf_len);
+ } else {
args[5] = 0;
+ }
ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp));
--
2.25.1
