Re: [U-Boot] amcc kilauea odd crashes

> I tested it and it's still failing. I dare say the patch makes things > worse. After about 20 hard resets the board didn't reach the u-boot > console a single time. > Markus, have you got access to BDI? ___ U-Boot mailing list U-Boot@lists.denx.de http

Re: [U-Boot] [PATCH] 440spe MQ initialization

> I have to admit that I am a little confused now. Are there now any patches > that should be applied to U-Boot regarding the MQ and/or the PLB arbiter > configuration? There is no patch that needs to be applied for PLB arbiter configuration. My earlier patch covered that. > It seems to me tha

Re: [U-Boot] [PATCH] 440spe MQ initialization

x27;s or Linus's tree. Thanks, Prodyut > From: Stefan Roese [mailto:[EMAIL PROTECTED] > Sent: Tue 9/23/2008 2:43 AM > To: Yuri Tikhonov > Cc: u-boot@lists.denx.de; Prodyut Hazarika; Olga Buchonina > Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization > On Tuesday

Re: [U-Boot] [PATCH] 440spe MQ initialization

Hi Yuri/Stefan, I remember duriing my testing that the default Read passing limit (RPML) and MCIF limit (WRCL) was 1. So there was no need to set these registers again to the same values. Thanks, Prodyut : Tue 9/23/2008 2:43 AM To: Yuri Tikhonov Cc: u-boot@lists.denx.de; Prodyut Hazarika

Re: [U-Boot] [PATCH] 440spe MQ initialization

n the program_memory_queue function. Thanks, Prodyut From: Stefan Roese [mailto:[EMAIL PROTECTED] Sent: Tue 9/23/2008 2:43 AM To: Yuri Tikhonov Cc: u-boot@lists.denx.de; Prodyut Hazarika; Olga Buchonina Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization

Re: [U-Boot] ppc4xx: Optimizations/Cleanups for IBM DDR2 MemoryController

> Just make sure to select "preformat" instead of "normal" > before you "insert" -> text file" on your patch. Thanks. I will try that next time I post any patch. Regards, Prodyut Hazarika ___ U

Re: [U-Boot] ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory Controller

change server. > And please don't indent the commit text and add one empty line before the > s-o-f line. I will take care of the that. Regards, Prodyut Hazarika == Staff S/W Engineer AMCC == ___ U-Boot maili

[U-Boot] ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory Controller

>From bdc99201a532b040b3d346fca5acff8332d670e4 Mon Sep 17 00:00:00 2001 From: Prodyut Hazarika <[EMAIL PROTECTED]> Date: Wed, 27 Aug 2008 16:26:36 -0700 Subject: [PATCH] Optimizations/Cleanups for IBM DDR2 memory controller Removed Magic numbers from Initialization preload registers Te

[U-Boot] [PATCH] ppc4xx: Optimization for DDR2 initialization for IBM DDR2 memory controller

>From 5dd36e0d171286f59e4ca4e9eb2a040143b4ec33 Mon Sep 17 00:00:00 2001 From: Prodyut Hazarika <[EMAIL PROTECTED]> Date: Wed, 27 Aug 2008 14:51:08 -0700 Subject: [PATCH] Optimization for DDR2 initialization for IBM DDR2 memory controller Optimized values suggested by Hardware Tea

Re: [U-Boot] [PATCH] ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT

know which lines were the problem. I would like to know the problem so that it does not get repeated in future. Best regards, Prodyut Hazarika == Staff S/W Engineer AMCC == ___ U-Boot mailing list U-Boot@lists.d

[U-Boot] [PATCH] ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT

Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]> --- cpu/ppc4xx/44x_spd_ddr2.c | 27 --- cpu/ppc4xx/cpu_init.c

[U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and memory queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT

Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]> --- cpu/ppc4xx/44x_spd_ddr2.c | 27 --- cpu/ppc4xx/cpu_init.c | 16 ++- include/asm-ppc/ppc4xx-sdram.h | 48 ++--- include/pp

Re: [U-Boot] [PATCH] ppc4xx: Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors

lines doc should be updated. Best regards, Prodyut Hazarika = Staff S/W Engineer AMCC = CONFIDENTIALITY NOTICE: This e-mail message, including any attachments, is for the sole use of the intende

Re: [U-Boot] [PATCH] ppc4xx: Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors

^^ space here defined(CONFIG_440EPX) || defined(CONFIG_440GR) ^space here Please advice what is the best way to proceed. As you can see, this is certainly not my invention. Regards, Prodyut Hazarika ==

Re: [U-Boot] [PATCH] ppc4xx: Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors

Dear Wolfgang, Please see comments below. > > But then, you are changing good TAB chanracters that were used for > > vertical alignment into spaces. This is incorrect - please read the > > Coding Style requirements. > > > > Please do not do this. The problem is that lot of existing code use

Re: [U-Boot] [PATCH] ppc4xx: Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors

we don't have to duplicate > those defines in 2 headers. This has been a big problem in the past with the > ppc405.h and ppc440.h headers. I will move the PPC405EX to the beginning of the list and resubmit. Best regards, Prodyut Hazarika = Staff Software Engineer A

Re: [U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and Memory Queue settings for PPC 440SP/SPe and 460EX/GT/SX

e patch for the same. Also could you please let me know whether you applied the patch. Sorry for the line wrap issues - I will use git-send-email next time. Regards, Prodyut Hazarika === Staff S/W Engineer AMCC === ---

[U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and Memory Queue settings for PPC 440SP/SPe and 460EX/GT/SX

Read Pipeline depth should be set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors. Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors Please apply patch against next branch of Stefan's git tree. Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]&g

Re: [U-Boot] [PATCH] PPC4xx: PLB4 Arbiter and Memory Queue Optimizations

still we should probably clean this up now, that > we are busy with these PLB arbiter defines. So could you please change those defines to uppercase? Thanks. I will change all to uppercase and resubmit. Best Regards, Prodyut Hazarika Staff S/W Engineer AMCC ==

[U-Boot] [PATCH] PPC4xx: PLB4 Arbiter and Memory Queue Optimizations

CONFIG_PLB4_CROSSBAR_ARBITER_CORE for the above PPC4xx families, and to remove the duplicated code from board specfic files. Also, added register definitions for MemoryQueue related registers, and enabled Memory Queue optimizatios for 460EX/GT. Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]> ---