misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2);
> >> This will fail if CONFIG_MISC=n which is neither selected nor implied
> >> for RK3588.
> > Good catch, did not test that scenario, will fix in a v3.
> >
> >> I tested on multiple RK3588 Jaguar, and the commercial (RK3588) grade
> >> ones all showed RK3588 v0.
> >>
> >> The one industrial grade (RK3588J) showed RK3588J v1.
> > Thanks for confirming this works on a J-variant.
> >
> >> I'm really not sure what this version number is for. If even Kever
> >> doesn't know what it means, I am not sure it makes sense to print it?
> > For rk356x there is some special handling for cpu-version <> 0 in vendor
> > code, and DT describe a cpu-version nvmem cell, so thought it could be
> > useful debug information. However it may just cause more confusion since
> > there is no clear information on what the different cpu-version mean.
> >
> > Will drop the cpu-version information in a v3.
>
> Yes, this cpu-version does not help users, I think it may be one of the
> silicon version(
>
> The process may change in foundry), package version(change in package
> factory),
Apart from package number chip versions like RK3588, RK3588J and
RK3588M would be much beneficial when we boot multi-dtb from SPL and
load the respective silicon dtb in u-boot proper. So, chip numbers,
temperature (if possible) are useful like imx chips supported so far.
Thanks,
Jagan.
l, e.g. 0x35 0x82 or 0x35 0x88 */
> + ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2);
> + if (ret < 0) {
> + debug("%s: could not read cpu-code, ret=%d\n", __func__,
ret);
> + return 0;
> + }
> +
> + /* specification: SoC variant, e.g. 0xA for RK3588J and 0x13 for
RK3588S */
> + ret = misc_read(dev, RK3588_OTP_SPECIFICATION_OFFSET,
&specification, 1);
Any register to find the operating temperature of the chip?
Jagan.
bytes @ 0x0 Read: ERROR -5
> "
>
> Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories
> support")
> Signed-off-by: Marek Vasut
> ---
> Cc: Andre Przywara
> Cc: Ashok Reddy Soma
> Cc: Jagan Teki
> Cc: Michael Walle
> Cc: Michal
On Wed, Oct 30, 2024 at 4:15 PM Tudor Ambarus wrote:
>
>
>
> On 10/30/24 10:33 AM, Jagan Teki wrote:
> > Hi Marek,
> >
> > On Sun, Oct 27, 2024 at 1:48 AM Marek Vasut
> > wrote:
> >>
> >> Remove undocumented nor->addr_width == 3 test.
On Thu, Oct 10, 2024 at 8:59 AM Marek Vasut wrote:
>
> On 9/25/24 7:05 PM, Marek Vasut wrote:
> > On 9/11/24 1:05 PM, Marek Vasut wrote:
> >> On 8/30/24 3:36 PM, Jagan Teki wrote:
> >>> On Sun, Aug 25, 2024 at 5:58 AM Marek Vasut wrote:
> >>>
Hi Tom,
Please pull the below PR.
CI:
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/22949
thanks,
Jagan.
The following changes since commit 7af813341d5df064aeee764c31ffb50ffcdf4eb6:
Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog (2024-10-23
08:33:56 -0600
On Sun, Aug 25, 2024 at 5:58 AM Marek Vasut wrote:
>
> On 5/24/24 6:05 PM, Jagan Teki wrote:
> > On Mon, Mar 4, 2024 at 9:46 PM Marek Vasut wrote:
> >>
> >> Some Winbond SPI NORs have special SR3 register which is
> >> used among other things to contro
: Pre-PLL locking failed
inno_hdmi_phy phy@ff43: PHY: Failed to power on phy@ff43: -110.
failed to power on phy (ret=-110)
Fixes: aa2271184603 ("phy: rockchip: Add Rockchip INNO HDMI PHY driver")
Suggested-by: Jonas Karlman
Signed-off-by: Jagan Teki
---
drivers/phy/rockchip/phy-roc
al,usbkbd
Out: serial,vidconsole
Err: serial,vidconsole
Model: Firefly roc-rk3328-cc
Net: eth0: ethernet@ff54
Jagan.
On Mon, 27 May 2024 at 14:17, Quentin Schulz wrote:
>
> Hi Jagan,
>
> On 5/27/24 8:39 AM, Jagan Teki wrote:
> > Add support for USB OTG with UMS to program eMMC.
> >
> > Add it for Edgeble NCM6A, NCM6B.
> >
> > Signed-off-by: Jagan Teki
> > ---
&
Add support for USB OTG with UMS to program eMMC.
Add it for Edgeble NCM6A, NCM6B.
Signed-off-by: Jagan Teki
---
.../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi| 18 ++
.../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi| 18 ++
configs/neu6a-io-rk3588_defconfig
Edgeble NCM6B SoM has built-in eMMC so make sdhci has first boot
priority.
Fix it for NCM6A, NCM6B SoM.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 6 +-
arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 11 ++-
2 files changed, 7 insertions
On Mon, Feb 26, 2024 at 3:56 PM Dmitry Dunaev wrote:
>
> Added support for the Puya Semiconductor chips.
>
> The datasheet can be found here:
> https://www.puyasemi.com/h_xilie715.html
>
> Signed-off-by: Dmitry Dunaev
> ---
Applied to u-boot-spi/master
; > > + Tom Rini
> > > >
> > > > Do you have any comments for this series?
> > >
> > > Seems likely fine. Jagan, do you have time to put this in a PR for
> > > -next? Thanks.
> >
> > No reaction for quite a long time. Can you take it
On Mon, Feb 26, 2024 at 3:56 PM Dmitry Dunaev wrote:
>
> Added support for the Puya Semiconductor chips.
>
> The datasheet can be found here:
> https://www.puyasemi.com/h_xilie715.html
>
> Signed-off-by: Dmitry Dunaev
> ---
Reviewed-by: Jagan Teki
On Mon, Mar 4, 2024 at 9:46 PM Marek Vasut wrote:
>
> Some Winbond SPI NORs have special SR3 register which is
> used among other things to control whether non-standard
> "Individual Block/Sector Write Protection" (WPS bit)
> locking scheme is activated. This non-standard locking
> scheme is not s
Hi Anatolij,
On Mon, Feb 19, 2024 at 5:19 PM Jagan Teki wrote:
>
> Hi Anatolij,
>
> On Wed, Jan 17, 2024 at 1:22 PM Jagan Teki wrote:
> >
> > From: Jagan Teki
> >
> > Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would
> > sup
Hi Jonas,
On Mon, Feb 19, 2024 at 10:51 PM Jonas Karlman wrote:
>
> Hi Jagan,
>
> On 2024-01-17 08:51, Jagan Teki wrote:
> > Model: Firefly roc-rk3328-cc
> > DRAM: 1 GiB (effective 1022 MiB)
> > Video device 'vop@ff37' cannot allocate frame buffer
Hi Anatolij,
On Wed, Jan 17, 2024 at 1:22 PM Jagan Teki wrote:
>
> From: Jagan Teki
>
> Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would
> support external vendor PHY with DW HDMI chip.
>
> Support this vendor PHY by adding new platform PHY ops via DW H
lities from the controller point-of-view.
Jagan.
Hi Tom,
Please pull this PR.
Summary:
- Support Infineon S28HS02GT (Takahiro)
CI:
- https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/19467
thanks,
Jagan.
The following changes since commit 526a865fe4fea59fb2638726c26e39557eb97fdd:
Merge branch 'master-cleanup'
On Sun, Jan 28, 2024 at 9:25 PM Marek Vasut
wrote:
>
> From: Hai Pham
>
> Support RPC SPI on R8A779H0 V4M SoC.
>
> Reviewed-by: Paul Barker
> Signed-off-by: Hai Pham
> ---
> Cc: Jagan Teki
> Cc: Paul Barker
> ---
Reviewed-by: Jagan Teki
On Mon, Jan 29, 2024 at 6:57 PM Marek Vasut wrote:
>
> On 1/29/24 12:52, Jagan Teki wrote:
> > On Sun, Jan 28, 2024 at 9:25 PM Marek Vasut
> > wrote:
> >>
> >> From: Hai Pham
> >>
> >> Support RPC SPI on R8A779H0 V4M SoC.
> >&
r: Add support for locking on ISSI nor flashes
> mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes
> mtd: spi-nor: Add support for locking on Spansion nor flashes
Look like there are 3 or more topics are covered in single patch set,
please break them and send separate series.
Jagan
On Sun, Dec 31, 2023 at 11:27 PM Bhumkar, Tejas Arvind
wrote:
>
> [AMD Official Use Only - General]
>
> Hi Jagan,
>
> > -Original Message-
> > From: Jagan Teki
> > Sent: Wednesday, December 20, 2023 1:00 PM
> > To: Bhumkar, Tejas Arvind
>
wano
> ---
Reviewed-by: Jagan Teki
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
fpt_fixup()
> into one named s25_s28_post_bfpt_fixup().
>
> In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to
> be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing
> but it works actually (confirmed).
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
n s25_setup()
> so we can consolidate s28hx_t_setup() and s25_setup() into one named
> s25_s28_setup().
>
> spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be
> removed since there is no op that makes device busy state before setup.
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
tion and
> use nor->rdsr_dummy in octal DTR mode.
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
ncluding S28HS02GT, so
> we need to use CLPEF instead of CLSR.
>
> This change does not affect to S25x02GT which uses spansion_sr_ready() as
> S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30).
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
e. To support this,
> spansion_read_any_reg() needs to be reworked. Implementation is similar
> to existing read_sr() that already supports Octal DTR mode.
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
_erase_non_uniform().
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
>
> Signed-off-by: Takahiro Kuwano
> ---
Reviewed-by: Jagan Teki
On Tue, Jan 16, 2024 at 11:09 AM Ssunk wrote:
>
> Signed-off-by: Kankan Sun
> ---
Applied to u-boot-spi/master
On Sun, Jan 28, 2024 at 12:08 PM Tejas Bhumkar
wrote:
>
> The current implementation encounters issues when testing data ranging
> from 0 to 8 bytes. This was confirmed through testing with both ISSI
> (IS25WX256) and Micron (MT35XU02G) Flash exclusively in SDR mode.
>
> Upon investigation, it was
device with on-die
> ECC(8bit strength per 512bytes).
>
> Datasheet Links:
> - http://www.xtxtech.com/download/?AId=458
> - http://www.xtxtech.com/download/?AId=495
>
> Signed-off-by: Bruce Suen
> ---
This won't apply on my spi tree, maybe some out-of-master changes are stopping.
Jagan.
On Wed, Dec 27, 2023 at 9:58 PM Tejas Bhumkar
wrote:
>
> Added support for the ISSI OSPI flash part IS25LX512M.
> Initial testing was performed on the Tenzing-se1 board using
> SDR mode, covering basic erase, write, and readback operations.
>
> Signed-off-by: Tejas Bhumkar
> ---
Applied to u-boo
On Sun, Jan 28, 2024 at 9:25 PM Marek Vasut
wrote:
>
> From: Hai Pham
>
> Support RPC SPI on R8A779H0 V4M SoC.
>
> Reviewed-by: Paul Barker
> Signed-off-by: Hai Pham
> ---
> Cc: Jagan Teki
> Cc: Paul Barker
> ---
Applied to u-boot-spi/master
On Thu, Dec 21, 2023 at 3:43 PM Maksim Kiselev wrote:
>
> If even one byte is lost due to Rx FIFO overflow then we will never
> exit the read loop. Because the (priv->rx != priv->rx_end) condition will
> be always true.
>
> Let's check if Rx FIFO overflow occurred and exit the read loop
> in this
Hi Kever,
On Thu, Jan 18, 2024 at 9:09 AM Kever Yang wrote:
>
> Hi Jagan,
>
> Have you check the memory area, does it maybe overlap with other
> area? eg. heap, stack, malloc area and etc.
Start with GD all memory map seems proper before and after relocation.
I did load U
set
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
configs/roc-cc-rk3328_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 4ac3c9403b..4eef9016dc 100644
--- a/configs/roc-cc-rk3328_defconfig
++
Enable video console for Rockchip RK3328.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
include/configs/evb_rk3328.h| 5 +
include/configs/rk3328_common.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h
index
Enable and set the start address of pre-console buffer for RK3328.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
arch/arm/mach-rockchip/Kconfig | 1 +
common/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig
003ffcd5e8 failed at call 0021a5c4 (err=-28)
### ERROR ### Please RESET the board ###
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
arch/arm/dts/rk3328-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk33
From: Jagan Teki
Add support for Rockchip RK3328 VOP.
Require VOP cleanup before handoff to Linux by writing reset values to
WIN registers. Without this Linux VOP trigger page fault as below
[0.752016] Loading compiled-in X.509 certificates
[0.787796
From: Jagan Teki
Add Rockchip RK3328 HDMI Out driver.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop data
Changes for v2:
- none
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk3328_hdmi.c | 126 +++
drivers/video/rockchip/rk_hdmi.h
From: Jagan Teki
Add Rockchip INNO HDMI PHY driver for RK3328.
Reference from linux-next phy-rockchip-inno-hdmi driver.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1
From: Jagan Teki
Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/clk/rockchip/clk_rk3328.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk
From: Jagan Teki
VOP get and set clock would needed for VOP drivers.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- Add DCLK get rate
.../include/asm/arch-rockchip/cru_rk3328.h| 34 +++
drivers/clk/rockchip/clk_rk3328.c | 88
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for dsp registers.
Group the dsp register set via dsp_regs pointers so that dsp_offset
would point the dsp_regs to access for any changes in the offset value.
Signed-off-by: Jagan
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for win registers.
Group the win register set via win_regs pointers so that win_offset
would point the win_regs to access for any changes in the offset value.
Signed-off-by: Jagan
From: Jagan Teki
Get the regs from priv pointer instead of passing it an argument.
This would simplify the code and better readability.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/rockchip/rk_vop.c | 8
1 file changed, 4 insertions(+), 4 deletions
From: Jagan Teki
Add support for DW HDMI Setup HPD status.
Signed-off-by: Jagan Teki
---
Changes for v3:
- check hdmi->ops
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/driv
From: Jagan Teki
Add support for DW HDMI Read HPD status.
Signed-off-by: Jagan Teki
---
Changes for v3:
- check hdmi->ops
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/driv
From: Jagan Teki
HPD detection on some DW HDMIdesigned SoC's would need to read and
setup the HPD status explicitly.
So, extend the HPD detection code by adding the dw_hdmi_detect_hpd
function and move the default detection code caller there.
The new read and setup hdp will integrate the
From: Jagan Teki
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki
---
Changes for v3:
- drop data
- assign ops directly
Changes for v2:
- fix meson cfg
drivers/video/dw_hdmi.c
From: Jagan Teki
HDP is a hardware connector event, so detect the same once the
controller and attached PHY initialization are done.
Signed-off-by: Jagan Teki
---
Changes for v3, v2:
- none
drivers/video/rockchip/rk_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
From: Jagan Teki
Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would
support external vendor PHY with DW HDMI chip.
Support this vendor PHY by adding new platform PHY ops via DW HDMI
driver and call the respective generic phy from platform driver code.
This series tested in
layout
>
> Samuel Dionne-Riel (1):
> common: Kconfig: Fix CMD_BMP/BMP dependency
I'm trying to use this to print splash in SPL. Look like the SPL video
is not initialized in a general way like U-Boot proper does via
board_f.c in reserve_video() correct? do you have your board code to
initialize the video for SPL?
Jagan.
Hi Neil,
On Tue, Dec 19, 2023 at 5:21 PM Jagan Teki wrote:
>
> On Tue, Dec 19, 2023 at 2:34 PM Neil Armstrong
> wrote:
> >
> > On 18/12/2023 20:10, Jagan Teki wrote:
> > > From: Jagan Teki
> > >
> > > DW HDMI support Vendor PHY like Rockchip RK3
Hi Andy,
On Tue, Dec 19, 2023 at 2:17 PM Andy Yan wrote:
>
>
>
> Hi Jaqan，
> 在 2023-12-19 15:42:26，"Jagan Teki" 写道：
> >Hi Andy,
> >
> >On Tue, Dec 19, 2023 at 6:50 AM Andy Yan wrote:
> >>
> >>
> >> Hi Jaqan：
> &g
control controller fixup in flash, DTR read based on the DTR
flag I don't think adding extra CONFIG to hack the controller with
impact is.
Jagan,
On Mon, Dec 18, 2023 at 11:01 PM Maxim Kiselev wrote:
>
> Hello Jagan,
>
> пн, 18 дек. 2023 г. в 14:28, Jagan Teki :
> >
> > On Tue, Oct 17, 2023 at 12:35 PM Maksim Kiselev
> > wrote:
> > >
> > > If even one byte is lost due to Rx FIFO over
On Tue, Dec 19, 2023 at 2:34 PM Neil Armstrong
wrote:
>
> On 18/12/2023 20:10, Jagan Teki wrote:
> > From: Jagan Teki
> >
> > DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
> >
> > Extend the vendor phy handling by adding platform phy hook
Hi Andy,
On Tue, Dec 19, 2023 at 6:50 AM Andy Yan wrote:
>
>
> Hi Jaqan：
>
> At 2023-12-19 03:11:10, "Jagan Teki" wrote:
> >From: Jagan Teki
> >
> >Add support for Rockchip RK3328 VOP.
> >
> >Require VOP cleanup before handoff to Linux by
0 [ + ] rockchip_reset| `-- reset
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
configs/roc-cc-rk3328_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 4ac3c9403b..4eef9016dc 100644
--
Enable video console for Rockchip RK3328.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
include/configs/evb_rk3328.h| 5 +
include/configs/rk3328_common.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h
index
Enable and set the start address of pre-console buffer for RK3328.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/mach-rockchip/Kconfig | 1 +
common/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b
003ffcd5e8 failed at call 0021a5c4 (err=-28)
### ERROR ### Please RESET the board ###
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/dts/rk3328-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.d
From: Jagan Teki
Add support for Rockchip RK3328 VOP.
Require VOP cleanup before handoff to Linux by writing reset values to
WIN registers. Without this Linux VOP trigger page fault as below
[0.752016] Loading compiled-in X.509 certificates
[0.787796
From: Jagan Teki
Add Rockchip RK3328 HDMI Out driver.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/Makefile | 1 +
drivers/video/rockchip/rk3328_hdmi.c | 131 +++
drivers/video/rockchip/rk_hdmi.h | 3 +
3 files changed, 135
From: Jagan Teki
Add Rockchip INNO HDMI PHY driver for RK3328.
Reference from linux-next phy-rockchip-inno-hdmi driver.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers
From: Jagan Teki
Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/clk/rockchip/clk_rk3328.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk
From: Jagan Teki
VOP get and set clock would needed for VOP drivers.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Add DCLK get rate
.../include/asm/arch-rockchip/cru_rk3328.h| 34 +++
drivers/clk/rockchip/clk_rk3328.c | 88 ++-
2
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for dsp registers.
Group the dsp register set via dsp_regs pointers so that dsp_offset
would point the dsp_regs to access for any changes in the offset value.
Signed-off-by: Jagan
From: Jagan Teki
Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for win registers.
Group the win register set via win_regs pointers so that win_offset
would point the win_regs to access for any changes in the offset value.
Signed-off-by: Jagan
From: Jagan Teki
Get the regs from priv pointer instead of passing it an argument.
This would simplify the code and better readability.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/rk_vop.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
From: Jagan Teki
Add support for DW HDMI Setup HPD status.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 172e6b45a6
From: Jagan Teki
Add support for DW HDMI Read HPD status.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/dw_hdmi.c | 3 +++
include/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index 0a597206f0
From: Jagan Teki
HPD detection on some DW HDMIdesigned SoC's would need to read and
setup the HPD status explicitly.
So, extend the HPD detection code by adding the dw_hdmi_detect_hpd
function and move the default detection code caller there.
The new read and setup hdp will integrate the
From: Jagan Teki
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki
---
Changes for v2:
- fix meson cfg
drivers/video/dw_hdmi.c | 29 +++-
drivers/video
From: Jagan Teki
HDP is a hardware connector event, so detect the same once the
controller and attached PHY initialization are done.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/video/rockchip/rk_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a
From: Jagan Teki
Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would
support external vendor PHY with DW HDMI chip.
Support this vendor PHY by adding new platform PHY ops via DW HDMI
driver and call the respective generic phy from platform driver code.
This series tested in
On Mon, Dec 18, 2023 at 7:23 PM Robin Murphy wrote:
>
> On 2023-12-15 7:13 am, Kever Yang wrote:
> > Hi Jagan,
> >
> > On 2023/12/15 14:36, Jagan Teki wrote:
> >> Hi Heiko/Kerver/Anatoloj,
> >>
> >> On Mon, Dec 11, 2023 at 2:30 PM Jagan Teki
&g
Please don't top-post.
On Sun, Dec 17, 2023 at 4:15 AM Johan Jonker wrote:
>
> Hi Jagan,
>
> In your patch U-boot users must add a new file for each new Rockchip SoC.
>
> With the VOP2 introduction the VOP1 structures and functions are
> frozen/stabilized.
>
&g
On Wed, Oct 25, 2023 at 1:20 PM Kunihiko Hayashi
wrote:
>
> Currently the controller driver has maximum frequency in plat->frequency
> that is specified by "spi-max-frequency" DT property in the controller
> node. This is special to U-Boot and doesn't exist to Linux.
>
> spi {
> spi-ma
On Mon, Dec 4, 2023 at 2:23 PM Venkatesh Yadav Abbarapu
wrote:
>
> Add support for ISSI 256MB flash IS25LP02G. This part supports 4byte
> opcodes. It also supports dual and quad read.
>
> Signed-off-by: Sreekanth Sunnam
> Signed-off-by: Venkatesh Yadav Abbarapu
> ---
> Changes in v2:
> - Fixed t
On Mon, Nov 6, 2023 at 10:55 AM Venkatesh Yadav Abbarapu
wrote:
>
> Updating the block protection flags for Gigadevice gd25lx256e and
> ISSI is25wx256 OSPI flash parts.
>
> Signed-off-by: Venkatesh Yadav Abbarapu
> ---
Applied to u-boot-spi/master
On Thu, Dec 14, 2023 at 10:06 PM Tejas Bhumkar
wrote:
>
> Added support for Macronix OSPI flash parts MX25UM51345G
> and MX66UM2G45G, with initial testing conducted on the
> Tenzing-se1 board using STR mode for basic erase, write,
> and readback operations.
>
> Signed-off-by: Tejas Bhumkar
> ---
device with on-die
> ECC(8bit strength per 512bytes).
>
> Datasheet Links:
> - http://www.xtxtech.com/download/?AId=458
> - http://www.xtxtech.com/download/?AId=495
>
> Signed-off-by: Bruce Suen
> ---
Can you rebase and send on top of master? This won't apply.
Jagan.
BIT(3)
> +#define DW_SPI_INT_RXFIBIT(4)
> +#define DW_SPI_INT_MSTIBIT(5)
Why do we need unused macros?
Jagan.
On Fri, Oct 27, 2023 at 9:22 PM Stanislav Bolshakov
wrote:
>
> In accordance with the name of the function 'flash_is_unlocked()',
> it is implied that the return value will be either 'true' or 'false'.
> Moreover, calling this function from other parts of the program is
> based precisely on this f
Hi Tom,
Please pull this PR for next.
Summary:
- spi_nor_read_sfdp_dma_unsafe (Vaishnav)
- w25q01/02 (Jim)
CI:
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/18995
thanks,
Jagan.
The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63:
Prepare v2024.01
Hi Heiko/Kerver/Anatoloj,
On Mon, Dec 11, 2023 at 2:30 PM Jagan Teki wrote:
>
> Unlike RK3399, Sunxi/Meson DW HDMI the new Rockchip SoC Rk3328 would
> support external vendor PHY with DW HDMI chip.
>
> Support this vendor PHY by adding new platform PHY ops via DW HDMI
> d
On Mon, Oct 30, 2023 at 9:50 PM Jan Kiszka wrote:
>
> From: Jan Kiszka
>
> We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since
> day 1.
>
> Signed-off-by: Jan Kiszka
> ---
Applied to u-boot-spi/master
On Wed, Oct 18, 2023 at 9:08 AM Bruce Suen wrote:
>
> Add support for XTX XT55Q02G(1.8V,2Gbit).
>
> Signed-off-by: Bruce Suen
> ---
Applied to u-boot-spi/master
On Wed, Oct 18, 2023 at 12:59 AM Igor Prusov wrote:
>
> Adaptation of Linux commit d74c36480a67
>
> This patch adds support for ESMT F50L1G41LB and F50D1G41LB.
> It seems that ESMT likes to use random JEDEC ID from other vendors.
> Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c
On Fri, Aug 4, 2023 at 7:56 AM Jit Loon Lim wrote:
>
> From: Teik Heng Chong
>
> Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI
> configuration flash
>
> Signed-off-by: Teik Heng Chong
> ---
Applied to u-boot-spi/master
On Fri, Aug 4, 2023 at 7:57 AM Jit Loon Lim wrote:
>
> MT25QU01 OPN with 4B OPCODE support is currently not supported in
> source code and the driver reuses the definition for "n25q00a"
> which has the same silicon ID but is a slower part.
>
> Adding mt25u01g definition to the source code to suppo
1 - 100 of 1009 matches
Mail list logo
