[PATCH] mtd: rawnand: Add Macronix raw NAND controller driver

2021-09-14 Thread Zhengxun Li
format to use hardware correctly. 3. Remove the incompatible functions of Uboot. Signed-off-by: Zhengxun Li --- drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile| 1 + drivers/mtd/nand/raw/mxic_nand.c | 603 +++ 3 files changed, 610

Re: [PATCH v6 2/2] dt-bindings: add xilinx clocking wizard bindings

2021-06-16 Thread Zhengxun Li
Hi, Michal Simek 於 2021年6月16日 週三 上午10:05寫道: > > Hi, > > On 6/16/21 5:26 PM, Zhengxun Li wrote: > > Hi Sean, > > > > Thank you for your reply. > > > > Sean Anderson 於 2021年6月15日 週二 下午2:52寫道: > >> > >> > >> > >>

Re: [PATCH v6 2/2] dt-bindings: add xilinx clocking wizard bindings

2021-06-16 Thread Zhengxun Li
Hi Sean, Thank you for your reply. Sean Anderson 於 2021年6月15日 週二 下午2:52寫道: > > > > On 6/15/21 1:21 PM, Zhengxun Li wrote: > > Hi Michal, > > > > Sean Anderson 於 2021年6月11日 週五 下午3:07寫道: > >> > >> > >> > >> On 6/11/21 11:1

Re: [PATCH v6 2/2] dt-bindings: add xilinx clocking wizard bindings

2021-06-15 Thread Zhengxun Li
Hi Michal, Sean Anderson 於 2021年6月11日 週五 下午3:07寫道: > > > > On 6/11/21 11:10 AM, Zhengxun wrote: > > Add the devicetree binding for the xilinx clocking wizard. > > > > Signed-off-by: Zhengxun > > --- > > .../clock/xlnx,clocking-wizard.txt| 43 +++ > > 1 file c

Re: [PATCH v5 1/2] clk: zynq: Add clock wizard driver

2021-06-09 Thread Zhengxun Li
2) += clk_pic32.o > > obj-$(CONFIG_SANDBOX) += clk_sandbox.o > > diff --git a/drivers/clk/clk-xlnx-clock-wizard.c > > b/drivers/clk/clk-xlnx-clock-wizard.c > > new file mode 100644 > > index 00..70ee3af107 > > --- /dev/null > > +++ b/drivers/clk/clk-

Re: [PATCHv4,1/1] clk: zynq: Add clock wizard driver

2021-06-01 Thread Zhengxun Li
76c0eb27e6 >> --- /dev/null >> +++ b/drivers/clk/clk-xlnx-clock-wizard.c >> @@ -0,0 +1,177 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx 'Clocking Wizard' driver >> + * >> + * Copyright (c) 2021 Macronix Inc. >> +

Re: [Patch v2 1/2] clk: zynq: Add clock wizard driver

2021-05-07 Thread Zhengxun Li
Hi Michal, > Hi, > > snip. > + + priv->base = (void __iomem *)addr; >>> >>> But this assignment should be done in probe where you copy data from >>> plat structures to priv structures. >> >> Do you mean priv->base = (void __iomem *)plat->addr? > > yes. > > + + clk_in1 = dev

[Patch v2 2/2] board: Add Zynq Mxic picozed development board support

2021-04-29 Thread Zhengxun Li
Add the Zynq Mxic picozed development board support. Signed-off-by: Zhengxun Li --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/zynq-mxic-picozed.dts | 72 ++ 2 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynq

[Patch v2 1/2] clk: zynq: Add clock wizard driver

2021-04-29 Thread Zhengxun Li
set_rate to modify the frequency. Signed-off-by: Zhengxun Li --- drivers/clk/Kconfig | 9 +++ drivers/clk/Makefile| 1 + drivers/clk/clk-xlnx-clock-wizard.c | 152 3 files changed, 162 insertions(+) create mode 100644 drivers

[Patch v2 0/2] Add Xilinx clock wizard driver support

2021-04-29 Thread Zhengxun Li
This series add support to enable clock wizard for zynq platform. Changes in v2: - naming is aligned with linux - delete inappropriate description and code Zhengxun Li (2): clk: zynq: Add clock wizard driver board: Add Zynq Mxic picozed development board support arch/arm/dts/Makefile