LS1012AFRDM has 512MB of DDR.
So update Kernel load address as 0x9600 instead of default
0xa000.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Pratiyush Mohan Srivastava
---
Changes for v3:
- Rebased v2 patch to master
- Removed "initrd_high=0xf
Remove ramdisk_addr, ramdisk_size and update UART baud-rate.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Pratiyush Mohan Srivastava
---
Changes for v2 :
- Removed "initrd_high=0x\0"
- Removed console variable
include/configs/ls1012a_common.h | 4 --
From: Prabhakar Kushwaha
LS1012AFRDM has 512MB of DDR.
So update Kernel load address as 0x9600 instead of default
0xa000.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Pratiyush Mohan Srivastava
---
Changes for v2: Incorporated York's comments
- Removed ramdisk
Remove ramdisk_addr, ramdisk_size and update UART baud-rate.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Pratiyush Mohan Srivastava
---
include/configs/ls1012a_common.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/configs/ls1012a_common.h b/include
The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.
Signed-off-by: Pratiyush Mohan Srivastava
Reported-by: Jose Rivera
---
Changes for v3
Rebased to latest
The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.
Signed-off-by: Pratiyush Mohan Srivastava
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 14
LANE A of SerDes 2 Protocol 0x45 & 0x47 are SGMII9 and PCIE3
respectively.
So Update SerDes2 table for 0x45 & 0x47 protocol.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Pratiyush Mohan Srivastava
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 4 ++--
1 file changed, 2 in
From: Pratiyush Mohan Srivastava
Environment variable mcinitcmd is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during u-boot
booting.If this variable is not defined then macro MC_BOOT_ENV_VAR will be null
and
MC will not be booted and
Freescale's management complex (MC) uses System DDR for internal usage.
Increase used System DDR size from 256MB to 512 MB.
Signed-off-by: Pratiyush Mohan Srivastava
---
include/configs/ls2080a_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/co
Current code compares the return pointer of function qbman_cena_write_start
with NULL. Instead the value of the return pointer should be compared.
Signed-off-by: Pratiyush Mohan Srivastava
---
drivers/net/fsl-mc/dpio/qbman_portal.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
Freescale's LS2040A is a another personality of LS2080A SoC
without AIOP support consisting of 4 armv8 cores.
Signed-off-by: Pratiyush Mohan Srivastava
---
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 +
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
2 files changed, 2 inser
LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.
Signed-off-by: Pratiyush Mohan Srivastava
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch
Remove 115200 from "earlycon" to avoid loss of initial
log messages during linux kernel 4.1 bootup
Signed-off-by: Pratiyush Mohan Srivastava
---
include/configs/ls2080a_common.h | 2 +-
include/configs/ls2080ardb.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
di
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