Hi Tim,
Does your code base contain this patch[1]?
It probably addressed the same issue you meet.
[1] http://lists.denx.de/pipermail/u-boot/2014-February/174533.html
Regards,
Liu Ying
On Fri, Apr 03, 2015 at 04:59:57PM -0700, Tim Harvey wrote:
> It has been observed that some IMX6SDL SoC w
arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.
Signed-off-by: Liu Ying
---
drivers/video/ipu.h |8
drivers/video/ipu_disp.c | 27 ---
drivers/video/ipu_regs.h |3 +++
3
respectively.
Reported-by: Robin Gong
Acked-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying
---
Changes in v2:
-Added Robin Gong's ack.
drivers/video/ipu_regs.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
The structures ipu_cm and ipu_idmac contain some reserved arrays as
placeholders to make sure the trailing entries may point to the relevant
IPU registers. This patch corrects the size of the reserved arrays.
Changes in v2:
Added Robin Gong's ack.
Liu Ying (2):
video: ipu reg: Co
.
Reported-by: Robin Gong
Acked-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying
---
Changes in v2:
-Added Robin Gong's ack.
drivers/video/ipu_regs.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index b2
respectively.
Reported-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying
---
drivers/video/ipu_regs.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 73e57ea..b2481a4 100644
--- a/drivers/video/ipu_regs.h
+++ b
.
Reported-by: Robin Gong
Cc: Stefano Babic
Signed-off-by: Liu Ying
---
drivers/video/ipu_regs.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index b2481a4..21e9c99 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers
The structures ipu_cm and ipu_idmac contain some reserved arrays as
placeholders to make sure the trailing entries may point to the relevant
IPU registers. This patch corrects the size of the reserved arrays.
Liu Ying (2):
video: ipu reg: Correct reserved1 array size in struct ipu_cm
video
insertions(+)
>
Please fix the typo 'HYNC' in the commit head. It should be 'HSYNC'.
Regard,
Liu Ying
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Align with the context to use readl() to read the CCM_CCGR3
register with memory barrier instead of __raw_readl().
Signed-off-by: Liu Ying
---
board/freescale/mx6sabresd/mx6sabresd.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mx6sabresd
struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + int reg = readl(&iomux->gpr[2]);
> +
> + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
> + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0);
>
Should change the above logic to this to make sure both the LDB two
channels are disabled correc
From: Liu Ying
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
From: Liu Ying
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
Signed-off-by: Liu Ying
---
drivers/video/ipu_common.c |3 +++
1 files changed, 3
Hello, Anatolij,
Thanks for your review!
Best Regards,
Liu Ying
-Original Message-
From: Anatolij Gustschin [mailto:ag...@denx.de]
Sent: Thursday, January 27, 2011 7:29 AM
To: Liu Ying-B17645
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH 1/1] lcd: align fb writing address for
Hello,
I sent the following patch for view about 2 weeks ago and haven't got any
comment till now.
Could anyone help to give comments? Thanks.
Best Regards,
Liu Ying
-Original Message-
From: Liu Ying-B17645
Sent: Tuesday, January 11, 2011 3:30 PM
To: u-boot@lists.denx.de
Cc: Liu
CONFIG_SPLASH_SCREEN_ALIGN makes uboot support display
offset for splashimage. The framebuffer writing address
should be calculated according to different kinds of
framebuffer pixel format, i.e., bits per pixel value.
Signed-off-by: Liu Ying
---
common/lcd.c |2 +-
1 files changed, 1
CONFIG_SPLASH_SCREEN_ALIGN makes uboot support display
offset for splashimage. The framebuffer writing address
should be calculated according to different kinds of
framebuffer pixel format, i.e., bits per pixel value.
Signed-off-by: Liu Ying
---
common/lcd.c |2 +-
1 files changed, 1
. And, color space
conversion, color key, global alpha and local alpha are supported by
DP, too. I 'm not sure if these features are really needed in u-boot
or not.
Best Regards,
Liu Ying
> From: Stefano Babic
> Date: 2010/10/12
> To: u-boot@lists.denx.de
>
>
> Add framebuf
18 matches
Mail list logo
