Hi Tom,
The following changes since commit 3b4604a40b9fd61b87e9d059fc56f04d36f1a380:
board: vexpress_ca9x4: Enable D-cache and MMU (2025-07-16 10:56:28 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 1
On Thu, Jul 10, 2025 at 03:42:01AM +, Yao Zi wrote:
> Enable the network stack, the designware ethernet driver and
> corresponding glue driver. The Lichee Pi 4A board ships two RTL8211F
> phys, both attached to GMAC 0, thus support for Realtek phys and DM
> support for MDIO devices are enabled
On Thu, Jul 10, 2025 at 03:42:00AM +, Yao Zi wrote:
> TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
> that are capable of Gigabit operation. Describe them in SoC devicetree
> and enable them for Lichee Pi 4A.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/th1520-lich
On Thu, Jul 10, 2025 at 03:41:59AM +, Yao Zi wrote:
> The Designware IP integrated in TH1520 SoC requires extra clock
> configuration to operate correctly. The Linux kernel's T-Head DWMAC glue
> driver is ported and adapted to U-Boot's API.
>
> Signed-off-by: Yao Zi
> ---
> MAINTAINERS
On Thu, Jul 10, 2025 at 03:41:58AM +, Yao Zi wrote:
> TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
> range of memory, for example, the GMAC controllers. Let's limit the
> usable top of RAM below 4GiB to ensure DMA allocations are accessible to
> all peripherals.
>
>
On Thu, Jul 10, 2025 at 03:41:57AM +, Yao Zi wrote:
> Unlike the gate clocks which make no use of flags, most dividers in
> TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED
> flag. We couldn't simply ignore the flag, which causes wrong results
> when calculating the clock r
On Tue, Jul 08, 2025 at 06:31:21PM +0530, Eoin Dickson wrote:
> From: Eoin Dickson
>
> Add xfer function to PolarFire SoC coreqspi driver. The read and write
> operations are limited to one byte at a time instead of four as CMD18
> (multiple block read) reads garbage when four byte ops are enable
On Tue, Jul 08, 2025 at 06:31:20PM +0530, Eoin Dickson wrote:
> From: Eoin Dickson
>
> This driver adds GPIO support for PolarFire SoC family, this is required
> to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects
>
> Signed-off-by: Eoin Dickson
> ---
> drivers/gpio/Kconfi
On Wed, Jul 16, 2025 at 11:00:15AM -0600, Tom Rini wrote:
> [EXTERNAL MAIL]
> Date: Wed, 16 Jul 2025 11:00:15 -0600
> From: Tom Rini
> To: E Shattow
> Cc: Michal Simek , Martin Herren
> , u-boot@lists.denx.de, Andreas Schwab
> , Anup Patel , Atish Patra
> , Bin Meng , "Chia-Wei, Wang"
> , Co
On Mon, Jul 07, 2025 at 01:13:33PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> The loop in the icicle implementation of board_fit_config_name_match()
> runs strtok() to split off the vendor portion of the compatible string
> using , as the delimiter. strtok() modifies a string in place, s
On Mon, Jul 07, 2025 at 01:51:39PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> By default DEBUG_UART uses the SBI DBCN extension on S-Mode RISC-V
> platforms, but the Icicle Kit's firmware doesn't support it. Since
> DEBUG_UART is getting turned on automagically and this is somewhat
> mis
Hi Conor,
On Fri, Jul 04, 2025 at 11:40:21AM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]
> Date: Fri, 4 Jul 2025 11:40:21 +0100
> From: Conor Dooley
> To: Leo Liang
> CC: Conor Dooley , u-boot@lists.denx.de, Ivan Griffin
> , Cyril Jean , Tom
> Rini , Ilias Apalod
Hi Tom,
The following changes since commit c405bab7661dd60420e97a4edeb3162e9d7e02c5:
Merge tag 'mmc-next-2025-07-02' of
https://source.denx.de/u-boot/custodians/u-boot-mmc into next (2025-07-02
07:51:57 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodian
On Mon, Jun 23, 2025 at 12:51:36PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> The firmware on the Icicle is capable of providing a devicetree in a1 to
> U-Boot, but until now the devicetree has been packaged in a "payload" [1]
> alongside U-Boot (or other bootloaders/RTOSes) and appended
On Wed, Jun 18, 2025 at 09:54:57AM +, Yao Zi wrote:
> Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
> existing TH1520-based boards to ensure PINCTRL is enabled.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/cpu/th1520/Kconfig | 1 +
> configs/th1520_lpi4a_defconfig | 1
On Wed, Jun 18, 2025 at 09:54:56AM +, Yao Zi wrote:
> Describe the three pin controllers integrated in TH1520 SoC. Since we
> don't have support for clocks in the AON region, a dummy fixed-clock
> node is added to supply the pin controller locating in it.
>
> Signed-off-by: Yao Zi
> ---
> ar
On Wed, Jun 18, 2025 at 09:54:55AM +, Yao Zi wrote:
> The SoC pads of TH1520 are separated into three groups (AP 1, AP 2 and
> AON) controlled by independent pin controllers. This patch ports their
> driver from Linux kernel with most code for setting pinconf and pinmux
> kept as is.
>
> The d
On Fri, Jun 13, 2025 at 05:12:58PM +0100, Ben Dooks wrote:
> Test for big-endian either via __RISCVEB__ which migth be
> rather old, or check the BYTE_ORDER if the compiler defines
> it (which should be any modern gcc like v12)
>
> Signed-off-by: Ben Dooks
> ---
> arch/riscv/include/asm/byteorde
On Fri, Jun 06, 2025 at 04:28:04AM +, Yao Zi wrote:
> Setup core information and bring secondary HARTs up for a functional
> multi-core system.
>
> Signed-off-by: Yao Zi
> ---
> board/thead/th1520_lpi4a/spl.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Fri, Jun 06, 2025 at 04:28:03AM +, Yao Zi wrote:
> Preserve CLINT node for SPL, whose IPI functionality is essential for
> operation of a multi-core system.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/th1520.dtsi | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang
On Fri, Jun 06, 2025 at 04:28:02AM +, Yao Zi wrote:
> On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
> hardware, and the remaining HARTs are in reset states, requiring manual
> setup of reset address and deassertion to function normal. Introduce a
> routine to do the w
On Fri, Jun 06, 2025 at 04:28:01AM +, Yao Zi wrote:
> C910 cores integrated in TH1520 SoC provide various customized CSRs for
> configuring core behavior, including cache coherency and timing, branch
> predication, and clock gating for internal components.
>
> This patch sets them up for effic
On Fri, Jun 06, 2025 at 04:28:00AM +, Yao Zi wrote:
> Although timer component of the CLINT isn't fully compatible with the
> generic RISC-V ACLINT, the IPI component behaves the same.
>
> As the CLINT doesn't have corresponding riscv_aclint_timer driver
> available, let's try looking for a co
On Tue, Jul 01, 2025 at 07:04:26PM -0600, Tom Rini wrote:
> The cache driver here can only build on RISCV due to header
> dependencies. Express that requirement in Kconfig as well.
>
> Signed-off-by: Tom Rini
> ---
> drivers/cache/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo
On Sun, Jun 08, 2025 at 02:37:04AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> On Thu, Jun 05, 2025 at 02:05:06PM -0600, Tom Rini wrote:
> > On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
&
Hi Tom,
The following changes since commit e96b6c0c18c29fba63a1ceb21dc29afb9d9b2910:
Merge patch series "Remove as much arch/arm/dts/*.h as possible" (2025-06-06
13:54:42 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
for you
On Sun, Jun 08, 2025 at 02:37:04AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> On Thu, Jun 05, 2025 at 02:05:06PM -0600, Tom Rini wrote:
> > On Tue, Jun 03, 2025 at 02:45:21PM +0800, Leo Liang wrote:
> >
> > > Hi Tom,
> > >
&
Hi Tom,
The following changes since commit d45b1d4ac94710f88902adc2173d7930700e2869:
Merge tag 'u-boot-dfu-next-20250602' of
https://source.denx.de/u-boot/custodians/u-boot-dfu into next (2025-06-02
08:43:10 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/cust
On Fri, May 30, 2025 at 09:48:51AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Proper U-Boot for Lichee Pi 4A now runs in S mode instead of M mode,
> which means the extra firmware, OpenSBI, must be built and integrated
> in the image, and the vendor U-Boot cannot chainload the result image
> anymo
On Fri, May 30, 2025 at 09:48:50AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> RISC-V software usually expects S mode when leaving the firmware, e.g.
> UEFI applications could only run in S mode. Let's convert proper U-Boot
> of Lichee Pi 4A port to run in S mode.
>
> Signed-off-by: Yao Zi
> ---
On Fri, May 30, 2025 at 09:48:49AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Add an OpenSBI entry to the FIT image. As it expects an FDT to be
> passed, corresponding FDT entry is generated with of-list as well.
>
> As SPL now passes a full FDT for following stages, proper U-Boot image
> is pack
On Fri, May 30, 2025 at 09:48:48AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> These operations rely on a customized M-mode CSR, MHCR, which isn't
> available when running in S mode.
>
> Let's fallback to the generic weak stub when running in S mode to avoid
> illegal accesses.
>
> Signed-off-by:
On Fri, May 30, 2025 at 09:48:47AM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Symbols in spl.c only function correctly in SPL stage. Build the file
> for SPL only to avoid weak symbols in proper U-Boot being unexpectedly
> reloaded.
>
> Fixes: 5fe9ced3552 ("riscv: cpu: Add TH1520 CPU support")
>
On Thu, May 29, 2025 at 03:51:12PM +0530, Eoin Dickson wrote:
> [EXTERNAL MAIL]
>
> From: Eoin Dickson
>
> Add xfer function to PolarFire SoC coreqspi driver. The read and write
> operations are limited to one byte at a time instead of four as CMD18
> (multiple block read) reads garbage when fou
On Thu, May 29, 2025 at 03:51:11PM +0530, Eoin Dickson wrote:
> [EXTERNAL MAIL]
>
> From: Eoin Dickson
>
> This driver adds GPIO support for PolarFire SoC family, this is required
> to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects
>
> Signed-off-by: Eoin Dickson
> ---
>
Hi Eoin,
On Thu, May 22, 2025 at 07:40:01PM +0530, Eoin Dickson wrote:
> [EXTERNAL MAIL]
>
> From: Eoin Dickson
>
> Enable CONFIG_MPFS_GPIO, CONFIG_CMD_GPIO and CONFIG_DM_GPIO and
> CONFIG_MMC_SPI in the beaglev_fire_defconfig.
>
> Signed-off-by: Eoin Dickson
> ---
> configs/beaglev_fire_def
On Sun, May 25, 2025 at 12:42:48PM +0200, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
>
> On several RISC-V boards we have seen that 1 MiB is a insufficient value
> for CONFIG_SPL_SYS_MALLOC_SIZE.
>
> For instance qemu-riscv32_spl_defconfig fails booting because u-boot.itb
> exceeds 1 MiB.
>
>
On Fri, May 30, 2025 at 10:56:22AM +, Yao Zi wrote:
> Assign myself to develop U-Boot port of T-Head TH1520 SoC, and help
> maintain related code and review patches.
>
> Signed-off-by: Yao Zi
> ---
> MAINTAINERS | 7 +++
> 1 file changed, 7 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
Hi Tom,
The following changes since commit b22a276f039f818d5564bec6637071cfc8a7e432:
image: android: fix ramdisk default address (2025-05-30 13:44:05 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 31e
On Thu, May 29, 2025 at 03:30:51AM +, Mayuresh Chitale wrote:
> This reverts commit 14a4792a71db3561bea065415ac1f2ac69ef32b5 as
> discussed in [1].
>
> [1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html
>
> Signed-off-by: Mayuresh Chitale
> ---
> boot/image.c| 3 +--
> incl
On Thu, May 29, 2025 at 03:30:50AM +, Mayuresh Chitale wrote:
> This reverts commit 027a316828528da95a77d20632370b1bc2823f0b as
> discussed in [1].
>
> [1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html
>
> Signed-off-by: Mayuresh Chitale
> ---
> arch/riscv/dts/binman.dtsi
On Thu, May 29, 2025 at 03:30:49AM +, Mayuresh Chitale wrote:
> This reverts commit 37b0b22d8b7bbed6aa95b6daed06dcbf4a66f211 as
> discussed in [1].
>
> [1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html
>
> Signed-off-by: Mayuresh Chitale
> ---
> arch/riscv/lib/bootm.c | 4
On Thu, May 22, 2025 at 08:45:59AM -0600, Tom Rini wrote:
> On Thu, May 22, 2025 at 12:28:18PM +0100, Conor Dooley wrote:
> > On Wed, May 21, 2025 at 12:39:50PM -0600, Tom Rini wrote:
> > > On Wed, 21 May 2025 17:50:03 +0800, Leo Liang wrote:
> > >
> > >
Hi Tom,
The following changes since commit a3e09b24ffd4429909604f1b28455b44306edbaa:
Merge tag 'mmc-2025-05-20' of
https://source.denx.de/u-boot/custodians/u-boot-mmc (2025-05-20 08:35:31 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.g
On Fri, May 16, 2025 at 03:05:25AM +, Yao Zi wrote:
> Describe the newly-supported clock controller of TH1520 in SoC
> devicetree, replace dummy clocks with the controller-supplied ones and
> add correct clocks for GPIO controllers.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/th1520-lic
On Fri, May 16, 2025 at 03:05:24AM +, Yao Zi wrote:
> The clock driver is essential for TH1520 SoCs to operate. Select the
> driver in SoC Kconfig entry.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/cpu/th1520/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang
On Fri, May 16, 2025 at 03:05:23AM +, Yao Zi wrote:
> The driver is adapted from Linux kernel's version of clk-th1520-ap.c,
> with only output clocks for external sensors, which are barely useful in
> bootloaders, removed.
>
> Same as the mainline driver, it currently lacks of ability to enabl
On Fri, May 16, 2025 at 03:05:22AM +, Yao Zi wrote:
> TH1520 SoC ships several IOPMPs protecting various on-chip peripherals.
> They must be configured before accessing the peripherals. Let's
> initialize them in SPL harts_early_init().
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/cpu/th1520
On Tue, May 13, 2025 at 09:04:55AM +, Yao Zi wrote:
> The BROM of TH1520 always initializes UART0's parent clock and
> configures the baudrate to 115200. Describe the clock frequency to make
> UART function correctly in SPL without introducing CCF.
>
> Signed-off-by: Yao Zi
> ---
> include/c
On Sat, May 03, 2025 at 04:52:52AM -0700, E Shattow wrote:
> Move unnecessary clock frequency assignment out of device-tree and into the
> board config header so that the ns16550 serial driver can successfully init
> during SPL after failing to resolve the parent clock from upstream dts. The
> seri
On Sat, Apr 26, 2025 at 05:00:56PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
> devicetree blob.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/th1520.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by
On Sat, Apr 26, 2025 at 05:03:21PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Support for eMMC, SD card, GPIO and SPL have been available in LPi4A
> port. Update the documentation of support status and build
> instructions.
>
> Signed-off-by: Yao Zi
> ---
> doc/board/thead/lpi4a.rst | 58 ++
On Sat, Apr 26, 2025 at 05:03:20PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Adjust Kconfig and defconfig and add SPL initialization code for
> Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
> earlier. The board devicetree is changed to use TH1520 binman
> configuration to
On Sat, Apr 26, 2025 at 05:00:57PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Add binman configuration for TH1520 SoC, whose BROM loads the image
> combined into SRAM and directly jumps to it. The configuration creates
> u-boot-with-spl.bin where the SPL code locates at the start and the DDR
> fir
On Sat, Apr 26, 2025 at 05:00:55PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Memory node is necessary for TH1520 SPL to configure size and base
> address of DRAM. Let's preserve it in SPL devicetree blob.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 +
> 1
On Sat, Apr 26, 2025 at 05:00:54PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
> them in SPL devicetree blob with bootph-pre-ram property.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/th1520.dtsi | 6 ++
> 1 file chang
On Sat, Apr 26, 2025 at 05:09:16PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> On Sat, Apr 26, 2025 at 04:56:58PM +, Yao Zi wrote:
> > This patch cleans the vendor code of DDR initialization up, converts the
> > driver to fit in DM framework and use a firmware[1] packaged by binman to
> > ship
On Sat, Apr 26, 2025 at 04:56:58PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> This patch cleans the vendor code of DDR initialization up, converts the
> driver to fit in DM framework and use a firmware[1] packaged by binman to
> ship PHY configuration.
>
> Currently the driver is only capable of
On Sat, Apr 26, 2025 at 04:56:57PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Introduce the SoC-specific code and corresponding Kconfig entries for
> TH1520 SoC. Following features are implemented for TH1520,
>
> - Cache enable/disable through customized CSR
> - Invalidation of customized PMP ent
On Sat, Apr 26, 2025 at 04:56:56PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> The BROM of TH1520 always initializes its clock and configure the
> baudrate to 115200. Add a clock-frequency property to provide such
> information without introducing CCF to SPL.
>
> Signed-off-by: Yao Zi
> ---
> ar
On Sat, Apr 26, 2025 at 04:56:55PM +, Yao Zi wrote:
> [EXTERNAL MAIL]
>
> Designed before a standard set of cache management operations defined in
> RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
> customized extension XTheadCMO, which has been used in the CV1800B port
On Sat, May 03, 2025 at 02:25:54PM -0700, E Shattow wrote:
> - use upstream alias name for cpu and timer nodes
> - remove bootph-pre-ram hint from parent nodes
> - drop S7 cpu core "okay" status
>
> Signed-off-by: E Shattow
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 72 -
On Sun, Apr 27, 2025 at 02:50:11PM +, Yao Zi wrote:
> Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer
> which is defined with register qualifier into constants, breaking
> various components.
>
> This patch defines gd as a macro when building with Clang or LTO, which
>
On Fri, Apr 04, 2025 at 02:48:56PM +, Mayuresh Chitale wrote:
> Select between the 32-bit or 64-bit arch type for the image headers
> depending on how the build is configured.
>
> Signed-off-by: Mayuresh Chitale
> ---
> arch/riscv/dts/binman.dtsi | 14 ++
> arch/riscv/includ
On Thu, May 08, 2025 at 12:07:37AM +0530, Sughosh Ganu wrote:
> [EXTERNAL MAIL]
>
> On Wed, 7 May 2025 at 21:18, Tom Rini wrote:
> >
> > On Wed, May 07, 2025 at 03:11:38PM +0530, Sughosh Ganu wrote:
> > > On Wed, 7 May 2025 at 13:19, Sughosh Ganu wrote:
> > > >
> > > > On Tue, 6 May 2025 at 16:3
On Sat, May 03, 2025 at 05:29:44AM -0700, E Shattow wrote:
> JH7110 drivers are missing support for CPU frequency scaling, so override
> upstream device-tree to use default clock rates for syscrg. This override
> duplicates a portion of jh7110-common-u-boot.dtsi file planned for removal.
>
> Signe
On Wed, May 07, 2025 at 06:17:16AM +0200, Heinrich Schuchardt wrote:
> Mention that RISC-V supports semihosting.
>
> Update SPDX identifier to current format.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> doc/usage/semihosting.rst | 21 -
> 1 file changed, 12 insertions(+),
On Mon, Apr 28, 2025 at 04:48:45AM +, Mayuresh Chitale wrote:
> Fix the erroneous header guard for insn-def.h to reflect the correct
> header name.
>
> Fixes: bfc8ca3f7f6 ("riscv: Add support for defining instructions")
> Signed-off-by: Mayuresh Chitale
> ---
> arch/riscv/include/asm/insn-de
On Sat, Apr 26, 2025 at 05:26:02PM +, Yao Zi wrote:
> Drop filename property for proper U-Boot entry since binman takes
> "u-boot-nodtb.bin" as the default filename for u-boot-nodtb entries.
>
> This follows efe9c12322b ("riscv: dts: binman.dtsi: Switch to
> u-boot-nodtb entry for proper U-Boo
Hi Tom,
The following changes since commit 10f48365112b164bee6564033ab682747efcb483:
Merge patch series "Add PCIe support for TI AM64 SoC" (2025-04-24 10:46:17
-0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch change
On Wed, Apr 23, 2025 at 02:28:51PM -0700, E Shattow wrote:
> Signed-off-by: E Shattow
> ---
> doc/board/starfive/visionfive2.rst | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang
On Mon, Apr 21, 2025 at 11:49:17PM -0700, E Shattow wrote:
> Refactor inside-out EEPROM-checking logic to better match the board-seeking
> callback and ordered list of targets from starfive_visionfive2_config since
> the JH7110 OF_UPSTREAM migration.
>
> Signed-off-by: E Shattow
> ---
> board/st
Hi Yao,
On Fri, Mar 07, 2025 at 01:13:41PM +, Yao Zi wrote:
> It's common for S-Mode proper U-Boot to retrieve a FDT blob along with
> taking control from SBI firmware. Add a weak version of
> board_fdt_blob_setup to make use of it by default, avoiding copy-pasting
> similar functions among bo
On Sat, Mar 29, 2025 at 08:48:00PM +0800, Huan Zhou wrote:
> Add pinctrl support in bananapi-f3 platform
>
> Signed-off-by: Huan Zhou
> ---
> configs/bananapi-f3_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Thu, Apr 03, 2025 at 06:28:37PM +0800, Minda Chen wrote:
> Add match N:starfive pattern to visionfive2 board. Now
> starfive pattern just related to JH7110 IC.
>
> Signed-off-by: Minda Chen
> ---
> board/starfive/visionfive2/MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Thu, Apr 03, 2025 at 04:28:16PM +0200, Heinrich Schuchardt wrote:
> The number of memory banks in QEMU is not bounded by 1.
>
> In this example we have two banks:
>
> qemu-system-riscv64 \
> -machine virt \
> -nographic \
> -m 8192 \
> -smp 8,sockets=2,cores=4,threads=1 \
>
On Sun, Mar 30, 2025 at 06:24:21PM +0200, Heinrich Schuchardt wrote:
> Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
> name") the StarFive VisionFive 2 board fails to boot.
>
> Before that patch the SPL debug UART showed warnings like:
>
> clk_register: failed to get
On Sat, Mar 29, 2025 at 08:47:59PM +0800, Huan Zhou wrote:
> Add pinctrl node in device tree and update
> in bananapi f3 dts.
>
> Signed-off-by: Huan Zhou
> ---
> arch/riscv/dts/k1-bananapi-f3.dts | 3 +++
> arch/riscv/dts/k1-pinctrl.dtsi| 19 +++
> arch/riscv/dts/k1.dtsi
Hi Tom,
The following changes since commit 3d8be1f5ec30180748259a251efe4f63c8b4b329:
Prepare v2025.05-rc5 (2025-03-24 20:00:24 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to b452ed448fb2ad44a4b0a07908
Hi Tom,
The following changes since commit d574229880378081691dc06c430424015be0740c:
Merge tag 'qcom-next-20250324' of
https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next
(2025-03-24 12:38:48 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/cus
Hi Yao,
On Fri, Mar 07, 2025 at 01:13:41PM +, Yao Zi wrote:
> It's common for S-Mode proper U-Boot to retrieve a FDT blob along with
> taking control from SBI firmware. Add a weak version of
> board_fdt_blob_setup to make use of it by default, avoiding copy-pasting
> similar functions among bo
On Tue, Mar 11, 2025 at 09:38:51AM +0800, Huan Zhou wrote:
> Add RESET_SPACEMIT_K1 option in config
>
> Signed-off-by: Huan Zhou
> ---
> arch/riscv/cpu/k1/Kconfig | 1 +
> configs/bananapi-f3_defconfig | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Tue, Mar 11, 2025 at 09:38:50AM +0800, Huan Zhou wrote:
> Add reset-controller in k1 device tree.
>
> Signed-off-by: Huan Zhou
> ---
> arch/riscv/dts/k1.dtsi | 15 +++
> 1 file changed, 15 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Tue, Mar 11, 2025 at 09:38:49AM +0800, Huan Zhou wrote:
> Add spacemit reset driver.
>
> Signed-off-by: Huan Zhou
> ---
> drivers/reset/Kconfig | 7 +
> drivers/reset/Makefile| 1 +
> drivers/reset/reset-spacemit-k1.c | 548
> ++
On Tue, Mar 11, 2025 at 09:38:48AM +0800, Huan Zhou wrote:
> Add dt-binding for reset driver.
>
> Signed-off-by: Huan Zhou
> ---
> include/dt-bindings/reset/spacemit-k1-reset.h | 118
> ++
> 1 file changed, 118 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Fri, Mar 07, 2025 at 05:09:22PM +, Yao Zi wrote:
> Introduced in commit 5a4e0625ac77 ("riscv: dts: sophgo: Add ethernet
> node"), eth_{csrclk,ptpclk} were used as placeholders for ethernet
> controller. As the real clock controller has been added, drop them to
> clean the devicetree up.
>
>
On Mon, Mar 10, 2025 at 09:47:48AM +0800, Jimmy Ho wrote:
> Remove CFG_SYS_SDRAM_BASE so that we can get DRAM base from dt instead of
> compile time config.
> Removing this config helps the u-boot more portable.
>
> Signed-off-by: Jimmy Ho
> ---
> include/configs/sifive-unleashed.h | 1 -
> inc
On Fri, Mar 07, 2025 at 01:13:41PM +, Yao Zi wrote:
> It's common for S-Mode proper U-Boot to retrieve a FDT blob along with
> taking control from SBI firmware. Add a weak version of
> board_fdt_blob_setup to make use of it by default, avoiding copy-pasting
> similar functions among boards.
>
Hi Tom,
The following changes since commit 409d37e869e91453d94319792e17d1d882259b49:
led: Fix next Coverity scan error (2025-03-04 12:07:23 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 6e71966fa8a5e
On Thu, Feb 27, 2025 at 02:47:33PM +, Yao Zi wrote:
> Availability of RISC-V SBI service implies a prior stage exists. As SBI
> firmware usually passes a FDT to the loaded program, let's select
> OF_HAS_PRIOR_STAGE if SBI is enabled.
>
> With previously added fallback version of board_fdt_blob
Hi Huan,
Please run scripts/checkpatch.pl against your patchset
and respin a v2 after all the warnings & errors are attended to.
Thanks,
Leo
On Tue, Mar 04, 2025 at 03:03:28PM +0800, Huan Zhou wrote:
> Add spacemit reset driver.
> ---
> drivers/reset/Kconfig | 7 +
> drivers/rese
On Thu, Feb 27, 2025 at 02:47:33PM +, Yao Zi wrote:
> Availability of RISC-V SBI service implies a prior stage exists. As SBI
> firmware usually passes a FDT to the loaded program, let's select
> OF_HAS_PRIOR_STAGE if SBI is enabled.
>
> With previously added fallback version of board_fdt_blob
On Thu, Feb 27, 2025 at 02:47:32PM +, Yao Zi wrote:
> The default version should work for both SiFive Unmatched and Unleashed.
>
> Signed-off-by: Yao Zi
> ---
> board/sifive/unleashed/unleashed.c | 11 ---
> board/sifive/unmatched/unmatched.c | 10 --
> 2 files changed, 21 de
On Thu, Feb 27, 2025 at 02:47:31PM +, Yao Zi wrote:
> The default version should work for Starfive VisionFive 2.
>
> Signed-off-by: Yao Zi
> ---
> board/starfive/visionfive2/starfive_visionfive2.c | 10 --
> 1 file changed, 10 deletions(-)
Reviewed-by: Leo Yu-Chi Liang
On Thu, Feb 27, 2025 at 02:47:30PM +, Yao Zi wrote:
> The default version should work for RISC-V QEMU.
>
> Signed-off-by: Yao Zi
> ---
> board/emulation/qemu-riscv/qemu-riscv.c | 8
> 1 file changed, 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang
On Thu, Feb 27, 2025 at 02:47:29PM +, Yao Zi wrote:
> It's common for S-Mode U-Boot to retrieve a FDT blob along with taking
> control from SBI firmware. Add a weak version of board_fdt_blob_setup to
> make use of it by default and avoid copy-pasting similar functions among
> boards.
>
> Signe
On Tue, Nov 12, 2024 at 11:26:44AM +0100, Heinrich Schuchardt wrote:
> Without 'nvme scan' the ESP on the NVMe drive is not found early.
> EFI variables cannot be persisted.
>
> Hit any key to stop autoboot: 0
> Cannot persist EFI variables without system partition
> ** Booting bootfl
On Sun, Mar 02, 2025 at 09:50:17AM +0100, Heinrich Schuchardt wrote:
> The zkr ISA extension can be used to generate random numbers. Since RVA22
> zkr is an optional ISA extension. It can be emulated by QEMU. Our RNG
> driver detects if the extension is usable during driver binding. Let's
> enable
Hi Tom,
The following changes since commit 7a45cb4ffeff034304789954bb222ddd7d02104a:
fs/erofs: fix an integer overflow in symlink resolution (2025-02-18 12:32:07
-0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch chan
On Mon, Feb 10, 2025 at 12:18:28PM +0100, Heinrich Schuchardt wrote:
> The configuration descriptions generated by binman contain the vendor
> device-tree directory. Instead of adding it to all match strings just strip
> it off.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> no change
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