Re: [U-Boot] PCIe bridge pci memory limit register problem

The extra lines and line wrap are a result of my cut and paste, won't happen again. Any comments on the logic change? -- Interphase- Designed to Perform, Designed to Last (R) Danny Waldron - Technical Support Phone - 214.654

[U-Boot] PCIe bridge pci memory limit register problem

(pci_mem->bus_lower-1) >> 16); } ---------- Interphase- Designed to Perform, Designed to Last (R) Danny Waldron - Technical Support Phone - 214.654.5244 -- Disc Gol