On Mon, Sep 30, 2024 at 04:59:41PM +0800, Kever Yang wrote:
>
> On 2024/9/19 21:15, Chris Morgan wrote:
> > On Thu, Sep 19, 2024 at 09:48:58AM +0800, Kever Yang wrote:
> > > Hi Chris,
> > >
> > > On 2024/9/18 21:38, Chris Morgan wrote:
> > > > O
On Tue, Sep 24, 2024 at 12:24:16PM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 9/23/24 7:36 PM, Chris Morgan wrote:
> > On Mon, Sep 23, 2024 at 01:21:01PM +0200, Quentin Schulz wrote:
> > > Hi Chris,
> > >
> > > On 9/19/24 4:00 PM, Chri
On Tue, Sep 24, 2024 at 11:19:49AM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 9/23/24 7:38 PM, Chris Morgan wrote:
> > On Mon, Sep 23, 2024 at 01:24:34PM +0200, Quentin Schulz wrote:
> > > Hi Chris,
> > >
> > > On 9/19/24 4:00 PM, Chri
solution I think is to get SCMI clk
and reset support in mainline A-TF, but unfortunately I don't know how
to do that at the moment.
Chris
>
> > Chris Morgan (4):
> > board: rockchip: Convert Anbernic RGxx3 to OF_UPSTREAM
> > board: rockchip: Add vdd_cpu reg fixup for
On Mon, Sep 23, 2024 at 01:24:34PM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 9/19/24 4:00 PM, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Enable the PD_VO power domain before driver access on the rk3568 SoC.
> >
> > Signed-off-by: Chris Morga
On Mon, Sep 23, 2024 at 01:21:01PM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 9/19/24 4:00 PM, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Some of the Powkiddy devices switched to using a different vendor for
> > the vdd_cpu regulator. Unfortunate
On Thu, Sep 19, 2024 at 09:48:58AM +0800, Kever Yang wrote:
> Hi Chris,
>
> On 2024/9/18 21:38, Chris Morgan wrote:
> > On Wed, Sep 18, 2024 at 11:06:34AM +0800, Kever Yang wrote:
> > > Hi Chris,
> > >
> > > Please update the subject with something
From: Chris Morgan
Enable the PD_VO power domain before driver access on the rk3568 SoC.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c
b/arch/arm/mach-rockchip/rk3568
From: Chris Morgan
Remove config options for ARM SCMI. It is not required to boot the
board and when using the most recent mainline A-TF it actually causes
the device to freeze during boot due to missing SCMI support.
Signed-off-by: Chris Morgan
---
configs/anbernic-rgxx3-rk3566_defconfig | 2
From: Chris Morgan
Refactor the board detection logic (again) to make it compatible with
the upstream device-trees, and switch to OF_UPSTREAM.
Now the device boots with the device-tree for the 353P, and then
loads the correct device tree (of 10) in the later stages of SPL.
Signed-off-by: Chris
From: Chris Morgan
Some of the Powkiddy devices switched to using a different vendor for
the vdd_cpu regulator. Unfortunately the device does not have a new
revision to denote this, so users have no way of knowing in advance.
Add code to detect if a device is present at addresses 0x1c or 0x40
From: Chris Morgan
Update the Anbernic RGxx3 "device" to use upstream device-trees,
add logic to detect a different vdd_cpu regulator, and implement a
fix to allow the panel auto-detection to run when using mainline
A-TF.
Note that *Linux* still cannot use mainline A-TF because of t
x27;m thinking
if I do though I can at least get rid of the memory barrier.
>
> On 2024/9/17 05:01, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > The current panel detection logic crashes when the device boots with
> > mainline A-TF, causing a reboot loop. I
From: Chris Morgan
Some of the Powkiddy devices switched to using a different vendor for
the vdd_cpu regulator. Unfortunately the device does not have a new
revision to denote this, so users have no way of knowing in advance.
Add code to detect if a device is present at addresses 0x1c or 0x40
From: Chris Morgan
The current panel detection logic crashes when the device boots with
mainline A-TF, causing a reboot loop. It turns out mainline A-TF
doesn't enable the VO power domain like the BSP A-TF did.
Set the VO domain on and use a memory barrier to ensure it is powered
up befo
From: Chris Morgan
Refactor the board detection logic (again) to make it compatible with
the upstream device-trees, and switch to OF_UPSTREAM.
Now the device boots with the device-tree for the 353P, and then
loads the correct device tree (of 10) in the later stages of SPL.
Signed-off-by: Chris
From: Chris Morgan
Update the Anbernic RGxx3 "device" to use upstream device-trees,
add logic to detect a different vdd_cpu regulator, and implement a
fix to allow the panel auto-detection to run when using mainline
A-TF.
Note that *Linux* still cannot use mainline A-TF because of t
From: Chris Morgan
The Anbernic RG35XX series of devices are based around an Allwinner
H700 SoC with 1GB of RAM, 2 SD cards, and multiple input buttons.
This bootloader has been tested on the Anbernic RG35XX-2024 and
RG35XX-H, but should be suitable for the entire lineup of H700 based
devices
From: Chris Morgan
Change the Anbernic RG35XX series to use the r_i2c bus for the PMIC
instead of the r_rsb bus. This is to keep the device tree consistent
as there are at least 3 devices (the RG35XX-SP, RG28XX, and RG40XX-H)
that have an external RTC on the r_i2c bus.
Link:
https
From: Chris Morgan
Add pinctrl nodes for the r_i2c node. Without the pinmux defined the
r_i2c bus may fail to work, possibly if the bootloader uses rsb mode
for the PMIC.
Link:
https://lore.kernel.org/linux-sunxi/172252952262.1669767.7675865282122079154.b4...@csie.org/
[ upstream commit
From: Chris Morgan
Correct the default TPR6 parameter based on suggestion from Mikhail
Kalashnikov. [1]
[1]
https://lore.kernel.org/u-boot/4c003cab-c8b8-484d-924d-084e71fe6...@gmail.com/
Fixes: 4b02f0120a4b ("sunxi: H616: add LPDDR4 DRAM support")
Suggested-by: Mikhail Kalashnikov
From: Jernej Skrabec
CSI1 channel (22) is missing and IOMMU (25) has priority flag set in
vendor bootloader. Fix that.
While at it, replace bandwidth flag with priority since original flag has
always value "true".
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/
bank groups too.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 31 +++---
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
From: Jernej Skrabec
When comparing configuration procedure to vendor driver, I noticed that
one command was out of order and that some delays were missing.
Fix that.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 10 +-
1 file
From: Chris Morgan
It seems that different dies need different PHY pin mapping. Select
alternatives at compile time.
Signed-off-by: Jernej Skrabec
[adapted to switch from runtime to compile time config]
Signed-off-by: Chris Morgan
---
arch/arm/mach-sunxi/Kconfig| 17
From: Jernej Skrabec
Adjust H616 LPDDR4 DRAM settings to be in line with vendor driver.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c| 33 +--
.../dram_timings/h616_lpddr4_2133.c | 2 +-
2 files changed, 24
From: Chris Morgan
Add support for the Anbernic RG35XX-2024.
This device is a handheld gaming console (series) based around the
Anbernic H700 SoC. It comes with 1GB of RAM and multiple face buttons
for input.
Add support for the simplest model for now, and then iterate later to
add board
From: Chris Morgan
The Anbernic RG35XX series of devices are based around an Allwinner
H700 SoC with 1GB of RAM, 2 SD cards, and multiple input buttons.
This bootloader has been tested on the Anbernic RG35XX-2024 and
RG35XX-H, but should be suitable for the entire lineup of H700 based
devices
From: Chris Morgan
Change the Anbernic RG35XX series to use the r_i2c bus for the PMIC
instead of the r_rsb bus. This is to keep the device tree consistent
as there are at least 3 devices (the RG35XX-SP, RG28XX, and RG40XX-H)
that have an external RTC on the r_i2c bus.
Link:
https
From: Chris Morgan
Add pinctrl nodes for the r_i2c node. Without the pinmux defined the
r_i2c bus may fail to work, possibly if the bootloader uses rsb mode
for the PMIC.
Link:
https://lore.kernel.org/linux-sunxi/172252952262.1669767.7675865282122079154.b4...@csie.org/
[ upstream commit
From: Chris Morgan
Correct the default TPR6 parameter based on suggestion from Mikhail
Kalashnikov. [1]
[1]
https://lore.kernel.org/u-boot/4c003cab-c8b8-484d-924d-084e71fe6...@gmail.com/
Fixes: 4b02f0120a4b ("sunxi: H616: add LPDDR4 DRAM support")
Suggested-by: Mikhail Kalashnikov
From: Jernej Skrabec
CSI1 channel (22) is missing and IOMMU (25) has priority flag set in
vendor bootloader. Fix that.
While at it, replace bandwidth flag with priority since original flag has
always value "true".
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/
bank groups too.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 31 +++---
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
From: Jernej Skrabec
When comparing configuration procedure to vendor driver, I noticed that
one command was out of order and that some delays were missing.
Fix that.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 10 +-
1 file
From: Jernej Skrabec
It seems that different dies need different PHY pin mapping. Select
alternatives based on "bond ID".
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 59 +++---
1 file changed, 44 inserti
From: Jernej Skrabec
Adjust H616 LPDDR4 DRAM settings to be in line with vendor driver.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c| 33 +--
.../dram_timings/h616_lpddr4_2133.c | 2 +-
2 files changed, 24
From: Chris Morgan
Add support for the Anbernic RG35XX-2024.
This device is a handheld gaming console (series) based around the
Anbernic H700 SoC. It comes with 1GB of RAM and multiple face buttons
for input.
Add support for the simplest model for now, and then iterate later to
add board
On Wed, Aug 14, 2024 at 04:06:23PM -0500, Chris Morgan wrote:
> On Sat, Aug 03, 2024 at 03:29:17PM +0300, Mikhail Kalashnikov wrote:
> >
> > On 02.08.2024 01:55, Chris Morgan wrote:
> > > From: Jernej Skrabec
> > >
> > > Adjust H616 LPDDR4 DRAM
On Sat, Aug 03, 2024 at 03:29:17PM +0300, Mikhail Kalashnikov wrote:
>
> On 02.08.2024 01:55, Chris Morgan wrote:
> > From: Jernej Skrabec
> >
> > Adjust H616 LPDDR4 DRAM settings to be in line with vendor driver.
> >
> > Signed-off-by: Jernej
On Fri, Aug 02, 2024 at 04:08:39PM +0530, Sumit Garg wrote:
> Hi Andre,
>
> On Fri, 2 Aug 2024 at 15:27, Andre Przywara wrote:
> >
> > On Fri, 2 Aug 2024 12:24:56 +0530
> > Sumit Garg wrote:
> >
> > Hi Sumit,
> >
> > > Hi Chris,
> &
From: Chris Morgan
The Anbernic RG35XX series of devices are based around an Allwinner
H700 SoC with 1GB of RAM, 2 SD cards, and multiple input buttons.
This bootloader has been tested on the Anbernic RG35XX-2024 and
RG35XX-H, but should be suitable for the entire lineup of H700 based
devices
From: Jernej Skrabec
CSI1 channel (22) is missing and IOMMU (25) has priority flag set in
vendor bootloader. Fix that.
While at it, replace bandwidth flag with priority since original flag has
always value "true".
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/
From: Chris Morgan
Update the sun50i-h616.dtsi file from upstream linux, and include the
fix for selecting the pinctrl for the r_i2c bus from mainline:
7c9ea4ab7617 ("arm64: dts: allwinner: h616: Add r_i2c pinctrl nodes")
Signed-off-by: Chris Morgan
---
arch/arm/dts/sun50i
bank groups too.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 31 +++---
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
b/arch/arm/mach-sunxi/dram_sun50i_h616.c
From: Jernej Skrabec
When comparing configuration procedure to vendor driver, I noticed that
one command was out of order and that some delays were missing.
Fix that.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 10 +-
1 file
From: Jernej Skrabec
Adjust H616 LPDDR4 DRAM settings to be in line with vendor driver.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c| 35 +--
.../dram_timings/h616_lpddr4_2133.c | 2 +-
2 files changed, 26
From: Jernej Skrabec
It seems that different dies need different PHY pin mapping. Select
alternatives based on "bond ID".
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 59 +++---
1 file changed, 44 inserti
From: Jernej Skrabec
Adjust H616 LPDDR3 DRAM settings to be in line with vendor driver.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +-
arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c | 2 +-
2 files changed, 2 insertions(+), 2
From: Jernej Skrabec
Adjust H616 DDR3 DRAM settings to be in line with vendor driver.
Signed-off-by: Jernej Skrabec
Tested-by: Chris Morgan
---
arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi
From: Chris Morgan
Add support for the Anbernic RG35XX-2024.
This device is a handheld gaming console (series) based around the
Anbernic H700 SoC. It comes with 1GB of RAM and multiple face buttons
for input.
Add support for the simplest model for now, and then iterate later to
add board
axp_init(void)
> -{
> - return pmic_bus_init();
> -}
> -
> -#if !CONFIG_IS_ENABLED(ARM_PSCI_FW) &&
> !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
> -int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const
> argv[])
> -{
> - pmic_bus_setbits(AXP717_SHUTDOWN, AXP717_POWEROFF);
> -
> - /* infinite loop during shutdown */
> - while (1) {}
> -
> - /* not reached */
> - return 0;
> -}
> -#endif
> --
> 2.35.8
>
I've been using this for the past week or so on my RG35XX-H for which
I've been testing some code and it has worked well for me.
Tested-by: Chris Morgan
t; configs/nova-rk3588s_defconfig| 69 +++
>
> Here's the defconfig file, but:
>
> > > @@ -0,0 +1,6 @@
> > > +INDIEDROID-NOVA-RK3588
> > > +M: Chris Morgan
> > > +S: Maintained
> > > +F:
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
On Thu, May 23, 2024 at 11:47:41AM +0800, Kever Yang wrote:
>
> On 2024/5/21 23:45, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > This reverts commit 41a60d0e5cef54a59596a58940fa7c9cf071034b.
> >
> > On some of the supported devices the adc detect cod
> >> +/*
> > >> + * Copyright 2024 Tim Harvey
> > >> + */
> > >> +#include
> > >> +#include
> > >> +#include
> > >> +
> > >> +int fdt_kaslrseed(void *fdt)
> > >> +{
> > >> +
On Thu, May 02, 2024 at 10:00:46PM +0200, Jonas Karlman wrote:
> Hi Chris,
>
> On 2024-05-02 21:34, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Some of the rgxx3 devices do not have a way to recover from a poor
> > flash of a bootloader to eMMC. Set the
From: Chris Morgan
Some of the rgxx3 devices do not have a way to recover from a poor
flash of a bootloader to eMMC. Set the device to always attempt to boot
from sdmmc0 first which ensures that we can override the boot from
emmc if we have a card present with a valid fit signature. The
From: Chris Morgan
This reverts commit 41a60d0e5cef54a59596a58940fa7c9cf071034b.
On some of the supported devices the adc detect code always returns
that the button has been pushed, and as a result the device will
not boot normally.
Signed-off-by: Chris Morgan
---
board/anbernic/rgxx3_rk3566
From: Chris Morgan
Set the rgxx3 device to boot from mmc0 first. This serves as a fallback
to allow us to recover from a bad U-Boot (or later) stage in a worst
case scenario. The code for an ADC button appears to have broke some
board revisions; this solution is much simpler and allows users to
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
From: Chris Morgan
The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
UART, ADC, eMMC, and SDMMC are tested to work in U-Boot and this
successfully boots mainline Linux.
Kernel commit:
e99adc97e21a ("arm64: dts: rockchip: Add Powkiddy X55")
Signed-off-by: Ch
From: Chris Morgan
The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
UART, ADC, eMMC, and SDMMC are tested to work in U-Boot and this
successfully boots mainline Linux.
Kernel commit:
e99adc97e21a ("arm64: dts: rockchip: Add Powkiddy X55")
Signed-off-by: Ch
From: Chris Morgan
Some of the rgxx3 devices do not have a way to recover from a poor
flash of a bootloader to eMMC. Set the device to always attempt to boot
from sdmmc0 first which ensures that we can override the boot from
emmc if we have a card present with a valid U-Boot stage.
Signed-off
From: Chris Morgan
This reverts commit 41a60d0e5cef54a59596a58940fa7c9cf071034b.
On some of the supported devices the adc detect code always returns
that the button has been pushed, and as a result the device will
not boot normally.
Signed-off-by: Chris Morgan
---
board/anbernic/rgxx3_rk3566
From: Chris Morgan
Set the rgxx3 device to boot from mmc0 first. This serves as a fallback
to allow us to recover from a bad U-Boot (or later) stage in a worst
case scenario. The code for an ADC button appears to have broke some
board revisions; this solution is much simpler and allows users to
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
From: Chris Morgan
For root partitions, the UUID should still be random but the partition
type uuid should either be b921b045-1df0-41c3-af44-4c6f280d3fae for
aarch64 or 69dad710-2ce4-4e3c-b16c-21a1d49abed3 for aarch32. Correct
the attribute so it is the partition type that is hard coded and not
On Tue, Apr 02, 2024 at 06:38:59PM +0200, Quentin Schulz wrote:
> Hi Chris,
>
> On 4/1/24 20:14, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Allow RK3568 and RK3588 based boards to get the RAM bank configuration
> > from the ROCKCHIP_TPL stage instead
From: Chris Morgan
The Indiedroid Nova is a Rockchip RK3588S based SBC from Indiedroid.
Specifications:
Rockchip RK3588S SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
Optional eMMC
2x USB 2.0, 2x USB 3.0, 1x USB 3.0 C port with DP Alt
From: Chris Morgan
Switch all RK3568 and RK3588 boards to use the ATAGS based RAM bank
logic. This allows us to access all RAM when >= 4GB of RAM is available
while also automatically creating the memory holes when >= 16GB of RAM
is available.
Remove the board specific logic that prev
From: Chris Morgan
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices w
From: Chris Morgan
Use the ATAG info provided by the Rockchip binary TPL to identify
RAM banks on the RK3568 and RK3588 when using the ROCKCHIP_TPL binary.
This is needed because there are specific addresses that should not
be written to for all RK3588 based devices with >=16GB of RAM, writ
On Sat, Mar 30, 2024 at 11:53:38AM +0100, Jonas Karlman wrote:
> Hi Chris,
>
> On 2024-03-30 06:05, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Add SoC specific RAM bank logic for the rk3588 boards. This logic
> > works by reading the ATAGS crea
On Sat, Mar 30, 2024 at 12:00:46PM +0100, Jonas Karlman wrote:
> Hi Chris,
>
> On 2024-03-30 06:05, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Allow individual boards or SoCs to alter the RAM bank addition logic
> > by defining a __weak function th
From: Chris Morgan
Add SoC specific RAM bank logic for the rk3588 boards. This logic
works by reading the ATAGS created by the ROCKCHIP_TPL stage and
applies fixups on those to ensure we aren't stepping on any
reserved memory addresses.
The existing logic requires us to define memory hol
From: Chris Morgan
Allow individual boards or SoCs to alter the RAM bank addition logic
by defining a __weak function that these boards can then override
if needed. In the event this function fails, fallback to the default
detection logic.
Signed-off-by: Chris Morgan
---
arch/arm/mach
From: Chris Morgan
Use the ATAG info provided by the Rockchip binary TPL to identify
RAM banks on the RK3588 when using the ROCKCHIP_TPL binary.
This is needed because there are specific addresses that should not
be written to for all RK3588 based devices with >=16GB of RAM, writing
to th
On Thu, Mar 28, 2024 at 04:02:09PM -0400, Tom Rini wrote:
> On Wed, Mar 27, 2024 at 10:03:11AM -0500, Chris Morgan wrote:
> > On Wed, Mar 27, 2024 at 04:21:49PM +0200, Eugen Hristev wrote:
> > > On 3/27/24 15:32, Chris Morgan wrote:
> > > > On Wed, Mar 27, 2024 a
On Wed, Mar 27, 2024 at 04:21:49PM +0200, Eugen Hristev wrote:
> On 3/27/24 15:32, Chris Morgan wrote:
> > On Wed, Mar 27, 2024 at 06:32:06PM +0800, Kever Yang wrote:
> >> Hi Chris,
> >>
> >> The ATAGS is used for passing parameter from bootloader to
ode, guard it with
an #ifdef ROCKCHIP_TPL to only call it when using the Rockchip
specific RAM init (in the hopes that maybe one day we get our own
RAM init), and then replace existing code for boards like the Rock 5B
so that it no longer reserves these memory banks.
Thank you,
Chris.
>
&
From: Chris Morgan
Add support for defining the usable RAM from ATAGs provided by the
Rockchip binary TPL loader. This allows us to automatically account
for necessary memory holes on RK3588 devices with 16GB of RAM or
more, as well as ensure we can use the full amount of RAM available.
In the
From: Chris Morgan
Add support for parsing the ATAGs created by the Rockchip binary
RAM init. This ATAG parsing code was taken from the Rockchip BSP
U-Boot source and tested only on parsing the RAM specific ATAGs
for the RK3588.
Signed-off-by: Chris Morgan
---
arch/arm/include/asm/arch
From: Chris Morgan
Use the ATAG info provided by the Rockchip binary TPL to identify
RAM banks.
This is needed because there are specific addresses that should not
be written to for all RK3588 based devices with >=16GB of RAM, writing
to these addresses immediately results in a crash.
Ch
On Tue, Feb 06, 2024 at 10:53:13AM +0800, Kever Yang wrote:
>
> On 2024/2/6 02:58, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Add ADC button detect for early SPL stage for RGxx3 device. This is
> > important because on at least the RG353P and RG353V a c
On Tue, Feb 06, 2024 at 10:38:40AM +0800, Kever Yang wrote:
> Hi Chris,
>
> On 2024/2/6 02:58, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> > Move the necessary defines to the RGxx3 m
From: Chris Morgan
Add ADC button detect for early SPL stage for RGxx3 device. This is
important because on at least the RG353P and RG353V a clk pin is not
exposed that would allow us to take the eMMC out of the boot path.
Signed-off-by: Chris Morgan
---
board/anbernic/rgxx3_rk3566/rgxx3
From: Chris Morgan
Add support to the RGxx3 device for the Powkiddy RGB10MAX3. This device
is extremely similar to all the other devices and can use the same
bootloader with the same detection logic.
Signed-off-by: Chris Morgan
---
arch/arm/dts/rk3566-anbernic-rgxx3.dts | 9
From: Chris Morgan
Based on feedback from the mailing list while adding support for a new
device (the Powkiddy X55), correct the config options for the RGxx3
as well to remove unnecessary drivers and increase the SPL stack size.
Signed-off-by: Chris Morgan
---
configs/anbernic-rgxx3
From: Chris Morgan
This patch series is to clean up a few issues found with the RGxx3,
add support for a new device, and add a board specific ADC button
check routine to the SPL stage. The ADC button routine was part of
a previous patch series that was partially accepted, though making
the ADC
From: Chris Morgan
Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
Move the necessary defines to the RGxx3 main dts file.
Signed-off-by: Chris Morgan
---
.../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 ---
arch/arm/dts/rk3566-anbernic-rgxx3.dts
On Fri, Jan 19, 2024 at 05:01:38PM +0800, Kever Yang wrote:
> Hi Chris,
>
> On 2024/1/18 23:06, Chris Morgan wrote:
> > On Thu, Jan 18, 2024 at 03:20:52PM +0800, Kever Yang wrote:
> > > Hi Chris,
> > >
> > > On 2024/1/2 23:46, Chri
On Thu, Jan 18, 2024 at 03:20:52PM +0800, Kever Yang wrote:
> Hi Chris,
>
> On 2024/1/2 23:46, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Update the rockchip_dnl_key_pressed() so that it can run in
> > SPL. Also change the ADC channel to a define that
On Thu, Jan 18, 2024 at 02:37:04PM +0800, Kever Yang wrote:
> Hi Chris,
>
> On 2023/12/15 02:24, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
> > UART, ADC, eMMC, and SDMMC are
From: Chris Morgan
Update the RGxx3 documentation to note that it now supports the
RG-ARC-D, RG-ARC-S, Powkiddy RK2023, and Powkiddy RGB30. Also update
verbiage around panel detection to note that it is no longer hard coded
to the RG503.
Signed-off-by: Chris Morgan
---
doc/board/anbernic
From: Chris Morgan
Add support for the Anbernic RG-ARC-D, Anbernic RG-ARC-S, Powkiddy
RK2023, and Powkiddy RGB30 to the Anbernic RGxx3. While the Powkiddy
devices are manufactured by Powkiddy instead of Anbernic,
the hardware is so similar they can all use the same bootloader.
Signed-off-by
From: Chris Morgan
Allow all rockchip devices to use the hardware RNG to seed Linux
RNG.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/board.c | 32 ++
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 29
2 files changed, 32 insertions
From: Chris Morgan
Add support for users to enter recovery mode by holding the function
button when they power up the device.
Since the device has soldered eMMC and sometimes does not expose a clk
pin on the mainboard there is a small chance that a user who flashes a
bad bootloader may not be
From: Chris Morgan
Update the rockchip_dnl_key_pressed() so that it can run in
SPL. Also change the ADC channel to a define that can be
overridden by a board specific option.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/Makefile| 4 ++--
arch/arm/mach-rockchip/boot_mode.c | 11
From: Chris Morgan
Add kconfig options to enable ADC in SPL
Signed-off-by: Chris Morgan
---
common/spl/Kconfig | 7 +++
drivers/Makefile | 1 +
drivers/adc/Makefile | 2 +-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index
From: Chris Morgan
Make the inability to detect a panel using the auto detection code not
fail the entire boot process. This means that if the panel ID cannot
be read we don't set an environment variable for the panel, and if an
environment variable for the panel is not set we don't
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