From: Chin Liang See
Enabling cache and TLB maintenance broadcast through ACTLR as required
by Linux.
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/misc_gen5.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_gen5.c
b/arch
From: Chin Liang See
Enable Macronix flash support for Cyclone5 SoC
Signed-off-by: Chin Liang See
---
Changes for v2
- Undo change for is1, sr1500 and vining
---
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga_sockit_defconfig | 1 +
configs/socfpga_socrates_defconfig | 1 +
3
From: Chin Liang See
Ensure "spi-flash" is added into compatible string when there is
NOR flash being instantiated in DTS. Discovered "sf probe" command
without argument would hit error if spi-flash compatible string
is missing.
Signed-off-by: Chin Liang Se
From: Chin Liang See
Enable Macronix flash support for Cyclone5 SoC
Signed-off-by: Chin Liang See
---
configs/socfpga_cyclone5_defconfig| 1 +
configs/socfpga_is1_defconfig | 1 +
configs/socfpga_sockit_defconfig | 1 +
configs/socfpga_socrates_defconfig| 1 +
configs
From: Chin Liang See
Add SPL driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile| 4 +
arch/arm/mach-socfpga/include/mach/firewall_s10.h | 84 +
arch/arm/mach-socfpga/spl_s10.c | 138
From: Chin Liang See
Add MMU support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++
2 files changed, 72 insertions(+)
create mode 100644 arch/arm/mach-socfpga/mmu
From: Chin Liang See
Add timer support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/timer.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..23450b0
From: Chin Liang See
Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 5 +-
arch/arm/mach
From: Chin Liang See
Add build support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/Kconfig | 8 +-
arch/arm/mach-socfpga/Kconfig | 13 ++
configs/socfpga_stratix10_defconfig | 39 ++
include/configs/socfpga_stratix10_socdk.h
From: Chin Liang See
Add socdk board support for Stratix SoC
Signed-off-by: Chin Liang See
---
board/altera/stratix10-socdk/MAINTAINERS | 7 +++
board/altera/stratix10-socdk/Makefile| 7 +++
board/altera/stratix10-socdk/socfpga.c | 7 +++
3 files changed, 21 insertions
From: Chin Liang See
Device tree for Stratix10 SoC
Signed-off-by: Chin Liang See
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/socfpga_stratix10_socdk.dts | 180 +++
2 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 arch
From: Chin Liang See
Add DDR support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +
drivers/ddr/altera/Makefile| 1 +
drivers/ddr/altera/sdram_s10.c | 382
From: Chin Liang See
Add pinmux driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 2 +
.../arm/mach-socfpga/include/mach/system_manager.h | 5 +-
.../mach-socfpga/include/mach/system_manager_s10.h | 169
From: Chin Liang See
Add Reset Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
.../include/mach/reset_manager_arria10.h | 8 +-
.../mach
From: Chin Liang See
Add mailbox support for Stratix SoC
Signed-off-by: Ley Foon Tan
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++
arch/arm/mach-socfpga/mailbox_s10.c
From: Chin Liang See
Add Clock Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See
--
Changes in v2
- Declared defines for constant value used
- Fixed spacing and comments
---
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/clock_manager.c
From: Chin Liang See
Add misc support such as EMAC and cpu info printout for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/misc.c | 76
From: Chin Liang See
Add the base address map for Statix10 SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 ++
1 file changed, 56 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
diff --git
From: Chin Liang See
This patch series are enabling support for Stratix 10 SoC
Changes for v2
- Removed defines for base addresses that can be extracted from DTS
- Added CPU node plus MDIO node for Ethernet at DTS
- Added defines for constant value for readability
- Consolidated common code for
From: Chin Liang See
Add timer support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/timer.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c
index 253cde3..23450b0
From: Chin Liang See
Add mailbox support for Stratix SoC
Signed-off-by: Ley Foon Tan
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 108 ++
arch/arm/mach-socfpga/mailbox_s10.c
From: Chin Liang See
Add DDR support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/include/mach/sdram_s10.h | 333 +
drivers/ddr/altera/Makefile| 1 +
drivers/ddr/altera/sdram_s10.c | 382
From: Chin Liang See
Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 5 +-
arch/arm/mach
From: Chin Liang See
Add pinmux driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 2 +
.../arm/mach-socfpga/include/mach/system_manager.h | 5 +-
.../mach-socfpga/include/mach/system_manager_s10.h | 169
From: Chin Liang See
Add MMU support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 +++
2 files changed, 72 insertions(+)
create mode 100644 arch/arm/mach-socfpga/mmu
From: Chin Liang See
Add socdk board support for Stratix SoC
Signed-off-by: Chin Liang See
---
board/altera/stratix10-socdk/MAINTAINERS | 7 +++
board/altera/stratix10-socdk/Makefile| 7 +++
board/altera/stratix10-socdk/socfpga.c | 7 +++
3 files changed, 21 insertions
From: Chin Liang See
Add Clock Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/clock_manager.c | 4 +-
arch/arm/mach-socfpga/clock_manager_s10.c | 359
From: Chin Liang See
Add SPL driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 +
arch/arm/mach-socfpga/include/mach/firewall_s10.h | 84 +
arch
From: Chin Liang See
Add build support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/Kconfig | 8 +-
arch/arm/mach-socfpga/Kconfig | 13 ++
configs/socfpga_stratix10_defconfig | 39 ++
include/configs/socfpga_stratix10_socdk.h
From: Chin Liang See
Add misc support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/misc.c | 4 +
arch/arm/mach-socfpga/misc_s10.c | 165 +++
3 files changed, 170 insertions
From: Chin Liang See
Add Reset Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
.../mach-socfpga/include/mach/reset_manager_s10.h | 116
From: Chin Liang See
Device tree for Stratix10 SoC
Signed-off-by: Chin Liang See
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++
2 files changed, 143 insertions(+), 1 deletion(-)
create mode 100644 arch
From: Chin Liang See
Add the base address map for Statix10 SoC
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++
1 file changed, 58 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
diff --git
From: Chin Liang See
This patch series are enabling support for Stratix 10 SoC
Chin Liang See (14):
arm: socfpga: stratix10: Add base address map for Statix10 SoC
arm: dts: Add dts for Stratix10 SoC
arm: socfpga: stratix10: Add Clock Manager driver for Stratix10 SoC
arm: socfpga
_manager.h | 7 ++-
> arch/arm/mach-socfpga/misc.c | 27
> arch/arm/mach-socfpga/reset_clock_manager.S| 71
> ++
> 6 files changed, 134 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/reset_c
On Sel, 2016-11-29 at 10:55 +0530, Vignesh R wrote:
>
> On Monday 28 November 2016 07:45 PM, See, Chin Liang wrote:
> >
> > On Jum, 2016-11-25 at 17:51 +0100, Marek Vasut wrote:
> > >
> > > On 11/24/2016 06:35 AM, Vignesh R wrote:
> > > >
> > > >
> > > > According to Section 11.15.4.9.2 Indire
On Sab, 2016-11-26 at 08:43 +0530, Jagan Teki wrote:
> On Fri, Nov 25, 2016 at 10:07 PM, Champ, Andy
> wrote:
> >
> > Hi all,
> >
> >
> > in the table in drivers/mtd/spi/spi_flash_ids.c there is a flag
> > WR_QPP set against Macronix devices (including the ones Dumitru is
> > just adding).
> >
he code at 0x004c or
> > > 0x0050 , at which point the value of r0 and r1 registers is
> > > undefined. Moreover, jumping directly to the preloader entry
> > > point
> > > at address 0x will also fail, because address 0x004.
> > >
On Sel, 2016-10-18 at 06:00 +0200, Marek Vasut wrote:
> On 10/18/2016 05:22 AM, Chin Liang See wrote:
> >
> > On Sen, 2016-10-17 at 18:14 +0200, Marek Vasut wrote:
> > >
> > > On 10/17/2016 05:59 PM, Chin Liang See wrote:
> > > >
> > > >
On Sen, 2016-10-17 at 18:14 +0200, Marek Vasut wrote:
> On 10/17/2016 05:59 PM, Chin Liang See wrote:
> >
> > On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote:
> > >
> > > On 10/17/2016 05:28 PM, Chin Liang See wrote:
> > > >
> > > >
On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> On 10/17/2016 03:35 PM, See, Chin Liang wrote:
> >
> > On Min, 2016-10-16 at 17:34 +0200, Marek Vasut wrote:
> > >
> > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > >
> > > >
On Min, 2016-10-16 at 17:39 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> >
> > Add board folder
> directory
>
Will fix this.
> >
> > for Stratix 10 SoC development kit
> >
> > Signed-off-by: Chin Liang See
> >
On Sen, 2016-10-17 at 17:39 +0200, Marek Vasut wrote:
> On 10/17/2016 05:28 PM, Chin Liang See wrote:
> >
> > On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> > >
> > > On 10/17/2016 05:07 PM, Chin Liang See wrote:
> > > >
> > > >
On Min, 2016-10-16 at 17:41 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> >
> > Add SPL support for Stratix 10 SoC development kit
> >
> > Signed-off-by: Chin Liang See
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
>
On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> On 10/17/2016 05:14 PM, Chin Liang See wrote:
> >
> > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > >
> > > On 10/17/2016 03:35 PM, See, Chin Liang wrote:
> > > >
> > > >
On Sen, 2016-10-17 at 15:40 +0200, Marek Vasut wrote:
> On 10/17/2016 03:26 PM, See, Chin Liang wrote:
> >
> > On Min, 2016-10-16 at 17:31 +0200, Marek Vasut wrote:
> > >
> > > On 10/13/2016 10:32 AM, Chin Liang See wrote:
> > > >
> > > >
On Sen, 2016-10-17 at 17:20 +0200, Marek Vasut wrote:
> On 10/17/2016 05:07 PM, Chin Liang See wrote:
> >
> > On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> > >
> > > On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> > > >
> > > >
On Min, 2016-10-16 at 17:38 +0200, Marek Vasut wrote:
> On 10/13/2016 10:33 AM, Chin Liang See wrote:
> >
> > Disable the System Manager for Stratix 10 SoC as we are not
> > using this for SOCVP
> So I wonder, shouldn't we introduce some bool Kcon
On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote:
> On 10/17/2016 03:32 PM, See, Chin Liang wrote:
> >
> > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote:
> > >
> > > On 10/13/2016 10:33 AM, Chin Liang See wrote:
> > > >
> > > >
Add board folder for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
board/altera/stratix10-socdk/MAINTAINERS | 7 +++
board/altera/stratix10-socdk/Makefile| 7 +++
board/altera/stratix10-socdk
Add device tree for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
Acked-by: Marek Vasut
---
Changes for v3
- Changed to correct file mode
- Removed trampoline code
- Fixed the DDR size to 2GB and SDMMC
Add support for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/Kconfig | 4 +-
arch/arm/mach-socfpga/Kconfig | 10 ++
configs/socfpga_stratix10_defconfig
Disable the System Manager for Stratix 10 SoC as we are not
using this for SOCVP
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch
Add SPL support for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile | 13 -
arch/arm/mach-socfpga/spl.c| 13 -
2 files changed, 20 insertions(+), 6
Separate the misc.c to support both GEN5 SoC and Stratix 10 SoC.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/misc.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c
Separate the Reset Manager to support both GEN5 SoC and
Stratix 10 SoC.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
Acked-by: Marek Vasut
---
arch/arm/mach-socfpga/reset_manager.c | 12
1 file changed, 12 insertions
Disable the FPGA Manager for Stratix 10 SoC as we are not
using this for SOCVP
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch
Add memory map layout for Stratix 10 SoC
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile| 2 ++
arch/arm/mach-socfpga/mmu-arm64.c | 71 +++
2 files changed, 73
Add support for Stratix 10 SoC which is ARM64 based. This series
of patches are tested with Stratix 10 SOC Virtual Platform that
is available today.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
Chin Liang See (12):
arm: socfpga
Separate the Clock Manager to support both GEN5 SoC and
Stratix 10 SoC.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach
Add base address header file for Stratix10 SoC
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
Acked-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++
1 file changed, 48 insertions
Add Reset Manager registers structure for Stratix 10 SoC
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
Acked-by: Marek Vasut
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 32 ++
1 file changed, 32 insertions
Add support for Stratix 10 SoC which is ARM64 based. This series
of patches are tested with Stratix 10 SOC Virtual Platform that
is available today.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Tien Fong Chee
---
Chin Liang See (12):
arm: socfpga
On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> In order for SDRAM ECC to work correctly, the SDRAM needs to get
> zero'd which
> enables the ECC bit. By using the PL330 DMA to fill the SDRAM with
> zeroes,
> the operation is completed in ~1.2 seconds, versus ~14 sec
On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Add PL330_DMA entry.
>
> Signed-off-by: Dinh Nguyen
> ---
> drivers/dma/Kconfig | 4
> drivers/dma/Makefile | 1 +
> 2 files changed, 5 insertions(+)
>
Reviewed-by: Chin
On Mon, 2016-10-10 at 10:52 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Adopted from the Linux kernel PL330 DMA driver.
>
> Signed-off-by: Dinh Nguyen
> ---
> arch/arm/include/asm/pl330.h | 105 +
> drivers/dma/pl330.c | 942
> +++
> 2
On Wed, 2016-10-12 at 09:15 -0500, dumitru.bac...@intel.com wrote:
> From: Radu Bacrau
>
> This commit adds support for the Macronix MX66U51235F, MX66L1G45G and
> Micron MT25QU02G flash parts.
>
> Signed-off-by: Radu Bacrau
> Cc: Chin Liang See
> Cc: Dinh Nguyen
>
On Wed, 2016-09-21 at 11:59 +0200, Marek Vasut wrote:
> On 09/21/2016 04:35 AM, Chin Liang See wrote:
> > Update documentation to include the Cyclone V SoC Preloader
> > development flow. This include the update of Preloader handoff
> > through qts-filter.sh script. At same ti
Update documentation to include the Cyclone V SoC Preloader
development flow. This include the update of Preloader handoff
through qts-filter.sh script. At same time, removed the SDMMC
documentation as its using DM now.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
doc
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Add macro for all boards to avoid ifdef
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v3
- Removed ifdef by setting macro to
On Wed, 2016-09-21 at 03:20 +0200, Marek Vasut wrote:
> On 09/20/2016 08:05 AM, Chin Liang See wrote:
> > To enable configuration of sdr.ctrlcfg.extratime1 register which
> > enable
> > extra clocks for read to write command timing. This is critical to
> > ensure
On Tue, 2016-09-20 at 09:52 +0200, Marek Vasut wrote:
> On 09/20/2016 07:37 AM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote:
> > > On 09/19/2016 12:12 PM, Chin Liang See wrote:
> > > > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See
Cc: Marek Vasut
Cc: Dinh Nguyen
---
Changes for v2
- Removed v1 patches #2 to #9 as no
On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote:
> On 09/19/2016 12:11 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:26 AM, Chin Liang See wrote:
> > > > To enable configuration of sdr.ctrlcfg.ext
On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote:
> On 09/19/2016 12:12 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > > > Adding new handoff for SDRAM ctrcfg.extratime1
On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
>
> Same comment as 2/9 applies to the rest
Yup, we just need 1/
On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
>
> Same comment as 2/9
Yup, this patch is not required.
Thanks
Chin
On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > required for stabil LPDDR2 operation
>
> ... stable ...
>
> Isn't SoCDK using DDR3 DRAM ?
Yah, y
On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
> On 09/15/2016 09:26 AM, Chin Liang See wrote:
> > To enable configuration of sdr.ctrlcfg.extratime1 register which
> > enable
> > extra clocks for read to write command timing. This is critical to
> > ensure
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/sr1500/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index edbaf89
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/terasic/sockit/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/terasic/sockit/qts/sdram_config.h
b/board/terasic/sockit/qts
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h
b/board/terasic/de0
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/samtec/vining_fpga/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/samtec/vining_fpga/qts/sdram_config.h
b/board/samtec
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/is1/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 67ea1ec..aad7dce
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/ebv/socrates/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/ebv/socrates/qts/sdram_config.h
b/board/ebv/socrates/qts
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/denx/mcvevk/qts/sdram_config.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/denx/mcvevk/qts/sdram_config.h
b/board/denx/mcvevk/qts/sdram_config.h
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation
Signed-off-by: Chin Liang See
---
board/altera/arria5-socdk/qts/sdram_config.h | 3 +++
board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/board
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See
---
arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++-
arch/arm/mach-socfpga/qts
On Tue, 2016-09-06 at 09:29 -0500, Dinh Nguyen wrote:
>
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add base address header file for Stratix10 SoC
> >
> > Signed-off-by: Chin Liang See
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
> > C
On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote:
> On 09/06/2016 11:18 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Add support for Stratix 10 SoC development kit
On Tue, 2016-09-06 at 09:30 -0500, Dinh Nguyen wrote:
>
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add board folder for Stratix 10 SoC development kit
> >
> > Signed-off-by: Chin Liang See
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
> > C
On Tue, 2016-09-06 at 09:32 -0500, Dinh Nguyen wrote:
>
> On 09/06/2016 05:03 AM, Chin Liang See wrote:
> > Add support for Stratix 10 SoC development kit
> >
> > Signed-off-by: Chin Liang See
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
> > Cc
1 - 100 of 748 matches
Mail list logo
