[PATCH v3 3/3] drivers/crypto: aspeed: Add Caliptra ECDSA384 support

Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use. This patch is verified by the FIT signature verification using the "sha384,ecdsa384" algorithm. Signed-off-by: Chia-Wei Wang Reviewed-by: S

[PATCH v3 2/3] image-fit-sig: Remove padding check

e info->padding check from the upper, general layer. Signed-off-by: Chia-Wei Wang Reviewed-by: Simon Glass --- boot/image-fit-sig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index 35873b1fb0e..a121de60ae2 100644 --- a/boot/image-

[PATCH v3 1/3] lib: ecdsa: Add ECDSA384 support

Add ECDSA384 algorithm support for image signing and verification. Signed-off-by: Chia-Wei Wang Reviewed-by: Simon Glass --- include/u-boot/ecdsa.h | 1 + lib/ecdsa/ecdsa-verify.c | 14 +++--- tools/image-sig-host.c | 7 +++ 3 files changed, 19 insertions(+), 3 deletions

[PATCH v3 0/3] aspeed: ast2700: Add Caliptra ECDSA driver

- revise errno and error message as suggested by Simon - collect Reviewed-by tags Chia-Wei Wang (3): lib: ecdsa: Add ECDSA384 support image-fit-sig: Remove padding check drivers/crypto: aspeed: Add Caliptra ECDSA384 support boot/image-fit-sig.c| 2 +- drivers/crypto/aspeed

[PATCH v2 3/4] image-fit-sig: Remove padding check

e info->padding check from the upper, general layer. Signed-off-by: Chia-Wei Wang Reviewed-by: Simon Glass --- boot/image-fit-sig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index fe328df4a85..d06e6cc8ed6 100644 --- a/boot/image-

[PATCH v2 1/4] lib: ecdsa: Add ECDSA384 support

Add ECDSA384 algorithm support for image signing and verification. Signed-off-by: Chia-Wei Wang Reviewed-by: Simon Glass --- include/u-boot/ecdsa.h | 1 + lib/ecdsa/ecdsa-verify.c | 14 +++--- tools/image-sig-host.c | 7 +++ 3 files changed, 19 insertions(+), 3 deletions

[PATCH v2 2/4] lib: ecdsa: Create device tree node automatically

Both the signature and the public key are stored as DTS nodes in the FIT image and SPL/U-Boot DTBs. Like the RSA signing & verification do, this patch either creates the nodes or overwirte the content automatically. Signed-off-by: Chia-Wei Wang Reviewed-by: Simon Glass --- lib/ecdsa/e

[PATCH v2 4/4] drivers/crypto: aspeed: Add Caliptra ECDSA384 support

Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use. This patch is verified by the FIT signature verification using the "sha384,ecdsa384" algorithm. Signed-off-by: Chia-Wei Wang Reviewed-by: S

[PATCH v2 0/4] aspeed: ast2700: Add Caliptra ECDSA driver

v2 change: - revise the commit message of padding check removal for better explanation - remove redundant check in static function - revise errno and error message as suggested by Simon - collect Reviewed-by tags Chia-Wei Wang (4): lib: ecdsa: Add ECDSA384 support lib: ecdsa: Create d

[PATCH v2 8/8] configs: ibex-ast2700: Enable DRAM and timer driver

Enable the driver support for the DRAM and timer devices. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi Liang --- configs/ibex-ast2700_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index 22629b90489

[PATCH v2 5/8] timer: Add AST2700 IBEX timer support

Add the driver for the AST2700 Ibex timer, which uses CPU cycles as the timer count running at 200MHz. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi Liang --- drivers/timer/Kconfig | 6 + drivers/timer/Makefile | 1 + drivers/timer/ast_ibex_timer.c | 45

[PATCH v2 6/8] board: ibex_ast2700: Add FMC header support

Define and parse the header of the First Mutable Code (FMC) of AST2700 SoCs at runtime phase. The FMC header contains the information to load prebuilt binaries required for device initialization such as DRAM and VGA. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv

[PATCH v2 4/8] riscv: Add AST2700 SoC initial platform support

AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi

[PATCH v2 3/8] riscv: u-boot-spl.lds: Remove _image_binary_end alignment

() searching for the DTB by _image_binary_end will return the "Missing DTB" error. As the real DTB starting point does not align to a 8-bytes address like _image_binary_end does. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/u-boot-spl.lds | 2 -- 1 file

[PATCH v2 2/8] riscv: Make stack size shift configurable

Add prompt for STACK_SIZE_SHIFT to make it configurable. The default value remains 14 as usual. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index

[PATCH v2 1/8] riscv: Make A ISA extension selectable

Make the Atomic (A) ISA extension selectable. Thus CPUs such as Ibex without the A extension can be supported. Signed-off-by: Chia-Wei Wang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch

[PATCH v2 0/8] riscv: Add AST2700 platform support

- collect Reviewed-by and Acked-by tags - add the build document for ibex-ast2700 board as suggested Chia-Wei Wang (8): riscv: Make A ISA extension selectable riscv: Make stack size shift configurable riscv: u-boot-spl.lds: Remove _image_binary_end alignment riscv: Add AST2700 SoC initia

[PATCH 1/4] lib: ecdsa: Add ECDSA384 support

Add ECDSA384 algorithm support for image signing and verification. Signed-off-by: Chia-Wei Wang --- include/u-boot/ecdsa.h | 1 + lib/ecdsa/ecdsa-verify.c | 14 +++--- tools/image-sig-host.c | 7 +++ 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/include/u

[PATCH 0/4] aspeed: ast2700: Add Caliptra ECDSA driver

ECDSA public key storage is also revised by referring to RSA implementations. After the FIT common code revision, the driver is implemented for AST2700 to leverage the Caliptra ECDSA384 signature verification. These are verified by signed FIT images with the algorithm "sha384,ecdsa384".

[PATCH 4/4] drivers/crypto: aspeed: Add Caliptra ECDSA384 support

Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use. This patch is verified by the FIT signature verification using the "sha384,ecdsa384" algorithm. Signed-off-by: Chia-Wei Wang --- drivers/cry

[PATCH 2/4] lib: ecdsa: Create device tree node automatically

Both the signature and the public key are stored as DTS nodes in the FIT image and SPL/U-Boot DTBs. Like the RSA signing & verification do, this patch either creates the nodes or overwirte the content automatically. Signed-off-by: Chia-Wei Wang --- lib/ecdsa/ecdsa-libcrypto.c

[PATCH 3/4] image-fit-sig: Remove padding check

the upper, general layer. Signed-off-by: Chia-Wei Wang --- boot/image-fit-sig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index fe328df4a85..d06e6cc8ed6 100644 --- a/boot/image-fit-sig.c +++ b/boot/image-fit-sig.c @@ -95,7 +95,7

[PATCH] drivers/crypto: aspeed: Add Caliptra SHA ACC support

Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export a SHA accelerator interface for SoC to use. Note that CPTRA 1.0 supports only SHA384 and SHA512 and this patch is verified by the 'hash test sha384/sha512' commands. Signed-off-by: Chia-Wei Wang --- drivers/cry

[PATCH 8/8] configs: ibex-ast2700: Enable DRAM and timer driver

Enable the driver support for the DRAM and timer devices. Signed-off-by: Chia-Wei Wang --- configs/ibex-ast2700_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index 22629b9048..855615cc1e 100644 --- a/configs/ibex

[PATCH 6/8] board: ibex_ast2700: Add FMC header support

Define and parse the header of the First Mutable Code (FMC) of AST2700 SoCs at runtime phase. The FMC header contains the information to load prebuilt binaries required for device initialization such as DRAM and VGA. Signed-off-by: Chia-Wei Wang --- arch/riscv/include/asm/arch-ast2700

[PATCH 5/8] timer: Add AST2700 IBEX timer support

Add the driver for the AST2700 Ibex timer, which uses CPU cycles as the timer count running at 200MHz. Signed-off-by: Chia-Wei Wang --- drivers/timer/Kconfig | 6 + drivers/timer/Makefile | 1 + drivers/timer/ast_ibex_timer.c | 45 ++ 3

[PATCH 4/8] riscv: Add AST2700 SoC initial platform support

AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang --- arch/riscv/Kconfig

[PATCH 3/8] riscv: u-boot-spl.lds: Remove _image_binary_end alignment

() searching for the DTB by _image_binary_end will return the "Missing DTB" error. As the real DTB starting point does not align to a 8-bytes address like _image_binary_end does. Signed-off-by: Chia-Wei Wang --- arch/riscv/cpu/u-boot-spl.lds | 2 -- 1 file changed, 2 deletions(-) diff --

[PATCH 2/8] riscv: Make stack size shift configurable

Add prompt for STACK_SIZE_SHIFT to make it configurable. The default value remains 14 as usual. Signed-off-by: Chia-Wei Wang --- arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5859c5c54..d0476f975c 100644

[PATCH 1/8] riscv: Make A ISA extension selectable

Make the Atomic (A) ISA extension selectable. Thus CPUs such as Ibex without the A extension can be supported. Signed-off-by: Chia-Wei Wang --- arch/riscv/Kconfig | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c52

[PATCH 0/8] riscv: Add AST2700 platform support

tuning. As this MCU adopts the "small" configuration provided by Ibex and has limited SRAM space. In addition to the RV common code revision, the other patches provides the basic AST2700 platform code and DRAM/Timer drivers to succuessfully boot SPL and U-Boot on this Ibex-based MCU. Chi

[PATCH] ast2600: spl: Add boot mode detection

AST2600 supports boot from SPI(mmap), eMMC, and UART. This patch adds the boot mode detection and return the corresponding boot device type. Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 3 ++ arch/arm/mach-aspeed/ast2600/spl.c| 30

[PATCH] configs: ast2600: Move SPL bss section to DRAM space

ned-off-by: Chia-Wei Wang --- arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 94 + configs/evb-ast2600_defconfig | 3 + include/configs/evb_ast2600.h | 3 + 3 files changed, 100 insertions(+) create mode 100644 arch/arm/mach-aspeed/ast2600/u-bo

[PATCH v8 12/12] configs: ast2600: Boot kernel FIT in DRAM

. Therefore, we need to move the FIT image into DRAM before the booting. This patch update the CONFIG_BOOTCOMMAND to execute the pre-defined ENV variable which consists of FIT image copy to memory and booting. Signed-off-by: Chia-Wei Wang --- configs/evb-ast2600_defconfig | 2 +- include/configs

[PATCH v8 10/12] configs: ast2600-evb: Enable SPL FIT support

Enable SPL FIT image load and verification support. The HW accelerated SHA is also available with the newly added support of the HACE HW hash engine. The SPL thumb build is also enabled to keep the binary less than 64KB to fit into the Aspeed secure boot design. Signed-off-by: Chia-Wei Wang

[PATCH v8 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific

Move CONFIG_EXTRA_ENV_SETTINGS to board-specific configuration headers. Signed-off-by: Chia-Wei Wang --- include/configs/aspeed-common.h | 9 - include/configs/evb_ast2500.h | 7 +++ include/configs/evb_ast2600.h | 7 +++ 3 files changed, 14 insertions(+), 9 deletions

[PATCH v8 07/12] crypto: aspeed: Add AST2600 ACRY support

ACRY is designed to accelerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang --- drivers/crypto/aspeed/Kconfig | 10 ++ drivers/crypto/aspeed/Makefile | 1 + drivers/crypto/aspeed/aspeed_acry.c | 190 lib/rsa

[PATCH v8 08/12] ARM: dts: ast2600: Add ACRY to device tree

Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang Reviewed-by: Joel Stanley --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 9 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600

[PATCH v8 04/12] crypto: aspeed: Add AST2600 HACE support

From: Johnny Huang Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang Signed-off-by: Chia-Wei Wang --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1

[PATCH v8 09/12] ast2600: spl: Locate load buffer in DRAM space

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for spl_get_load_buffer() to allow generic SPL image loading code (e.g. FIT and Ymodem) to store data in DRAM. Signed-off-by: Chia-Wei Wang Reviewed-by: Joel Stanley --- arch/arm/mach-aspeed/ast2600/spl.c | 9 + 1 file changed, 1

[PATCH v8 06/12] clk: ast2600: Add RSACLK control for ACRY

Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine of ASPEED AST2600 SoCs. Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 1 + drivers/clk/aspeed/clk_ast2600.c | 24 +++ 2 files changed, 25 insertions(+) diff --git a/arch

[PATCH v8 05/12] ARM: dts: ast2600: Add HACE to device tree

From: Joel Stanley Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 8 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b

[PATCH v8 03/12] clk: ast2600: Add YCLK control for HACE

From: Joel Stanley Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++-- drivers/clk/aspeed/clk_ast2600.c | 22 +++ 2 files

[PATCH v8 02/12] aspeed: ast2600: Enlarge SRAM size

The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang Reviewed-by: Joel Stanley --- arch/arm/include/asm/arch-aspeed/platform.h | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v8 00/12] aspeed: Support secure boot chain with FIT image verification

d for HACE HW DMA issue by resetting HACE - add reset control for HACE device tree node - sync all of the HACE error message to use debug() v2: - update commit authors Chia-Wei Wang (9): image: fit: Fix parameter name for hash algorithm aspeed: ast2600: Enlarge SRAM size clk: ast2600: Add R

[PATCH v8 01/12] image: fit: Fix parameter name for hash algorithm

Fix inconsistent function parameter name of the hash algorithm. Signed-off-by: Chia-Wei Wang Fixes: 92055e138f2 ("image: Drop if/elseif hash selection in calculate_hash()") Reviewed-by: Joel Stanley Reviewed-by: Simon Glass --- common/image-fit.c | 4 ++-- 1 file changed, 2 insert

[PATCH next v7 08/12] ARM: dts: ast2600: Add ACRY to device tree

Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 9 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index adb80a30ef

[PATCH next v7 09/12] ast2600: spl: Locate load buffer in DRAM space

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for spl_get_load_buffer() to allow generic SPL image loading code (e.g. FIT and Ymodem) to store data in DRAM. Signed-off-by: Chia-Wei Wang --- arch/arm/mach-aspeed/ast2600/spl.c | 9 + 1 file changed, 1 insertion(+), 8 deletions

[PATCH next v7 04/12] crypto: aspeed: Add AST2600 HACE support

From: Johnny Huang Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang Signed-off-by: Chia-Wei Wang --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1

[PATCH next v7 12/12] configs: ast2600: Boot kernel FIT in DRAM

. Therefore, we need to move the FIT image into DRAM before the booting. This patch update the CONFIG_BOOTCOMMAND to execute the pre-defined ENV variable which consists of FIT image copy to memory and booting. Signed-off-by: Chia-Wei Wang --- configs/evb-ast2600_defconfig | 2 +- include/configs

[PATCH next v7 10/12] configs: ast2600-evb: Enable SPL FIT support

Enable SPL FIT image load and verification support. The HW accelerated SHA is also available with the newly added support of the HACE HW hash engine. The SPL thumb build is also enabled to keep the binary less than 64KB to fit into the Aspeed secure boot design. Signed-off-by: Chia-Wei Wang

[PATCH next v7 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific

Move CONFIG_EXTRA_ENV_SETTINGS to board-specific configuration headers. Signed-off-by: Chia-Wei Wang --- include/configs/aspeed-common.h | 9 - include/configs/evb_ast2500.h | 9 + include/configs/evb_ast2600.h | 9 + 3 files changed, 18 insertions(+), 9 deletions

[PATCH next v7 07/12] crypto: aspeed: Add AST2600 ACRY support

ACRY is deisnged to accerlerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang --- drivers/crypto/aspeed/Kconfig | 10 ++ drivers/crypto/aspeed/Makefile | 1 + drivers/crypto/aspeed/aspeed_acry.c | 190 lib/rsa

[PATCH next v7 05/12] ARM: dts: ast2600: Add HACE to device tree

From: Joel Stanley Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 8 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b

[PATCH next v7 06/12] clk: ast2600: Add RSACLK control for ACRY

. Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 1 + drivers/clk/aspeed/clk_ast2600.c | 22 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch

[PATCH next v7 03/12] clk: ast2600: Add YCLK control for HACE

From: Joel Stanley Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++-- drivers/clk/aspeed/clk_ast2600.c | 20 +++ 2 files

[PATCH next v7 00/12] aspeed: Support secure boot chain with FIT image verification

commit authors Chia-Wei Wang (9): image: fit: Fix parameter name for hash algorithm aspeed: ast2600: Enlarge SRAM size clk: ast2600: Add RSACLK control for ACRY crypto: aspeed: Add AST2600 ACRY support ARM: dts: ast2600: Add ACRY to device tree ast2600: spl: Locate load buffer in DRAM

[PATCH next v7 01/12] image: fit: Fix parameter name for hash algorithm

Fix inconsistent function parameter name of the hash algorithm. Signed-off-by: Chia-Wei Wang Fixes: 92055e138f2 ("image: Drop if/elseif hash selection in calculate_hash()") --- common/image-fit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/image-fit.

[PATCH next v7 02/12] aspeed: ast2600: Enlarge SRAM size

The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang --- arch/arm/include/asm/arch-aspeed/platform.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch

[PATCH next v6 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific

Move CONFIG_EXTRA_ENV_SETTINGS to board-specific configuration headers. Signed-off-by: Chia-Wei Wang --- include/configs/aspeed-common.h | 9 - include/configs/evb_ast2500.h | 9 + include/configs/evb_ast2600.h | 9 + 3 files changed, 18 insertions(+), 9 deletions

[PATCH next v6 04/12] crypto: aspeed: Add AST2600 HACE support

From: Johnny Huang Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang Signed-off-by: Chia-Wei Wang --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1

[PATCH next v6 12/12] configs: ast2600: Boot kernel FIT in DRAM

. Therefore, we need to move the FIT image into DRAM before the booting. This patch update the CONFIG_BOOTCOMMAND to execute the pre-defined ENV variable which consists of FIT image copy to memory and booting. Signed-off-by: Chia-Wei Wang --- configs/evb-ast2600_defconfig | 2 +- include/configs

[PATCH next v6 07/12] crypto: aspeed: Add AST2600 ACRY support

ACRY is deisnged to accerlerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang --- drivers/crypto/aspeed/Kconfig | 10 ++ drivers/crypto/aspeed/Makefile | 1 + drivers/crypto/aspeed/aspeed_acry.c | 182 lib/rsa

[PATCH next v6 09/12] ast2600: spl: Locate load buffer in DRAM space

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for spl_get_load_buffer() to allow generic SPL image loading code (e.g. FIT and Ymodem) to store data in DRAM. Signed-off-by: Chia-Wei Wang --- arch/arm/mach-aspeed/ast2600/spl.c | 9 + 1 file changed, 1 insertion(+), 8 deletions

[PATCH next v6 08/12] ARM: dts: ast2600: Add ACRY to device tree

Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 9 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index adb80a30ef

[PATCH next v6 10/12] configs: ast2600-evb: Enable SPL FIT support

Enable SPL FIT image load and verification support. The HW accelerated SHA is also available with the newly added support of the HACE HW hash engine. The SPL thumb build is also enabled to keep the binary less than 64KB to fit into the Aspeed secure boot design. Signed-off-by: Chia-Wei Wang

[PATCH next v6 06/12] clk: ast2600: Add RSACLK control for ACRY

. Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 1 + drivers/clk/aspeed/clk_ast2600.c | 22 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch

[PATCH next v6 05/12] ARM: dts: ast2600: Add HACE to device tree

From: Joel Stanley Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 8 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b

[PATCH next v6 00/12] aspeed: Support secure boot chain with FIT image verification

defconfig based on the new Kconfig of U-Boot next branch v3: - add SW work around for HACE HW DMA issue by resetting HACE - add reset control for HACE device tree node - sync all of the HACE error message to use debug() v2: - update commit authors Chia-Wei Wang (9): image: fit: Fix parameter

[PATCH next v6 03/12] clk: ast2600: Add YCLK control for HACE

From: Joel Stanley Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++-- drivers/clk/aspeed/clk_ast2600.c | 20 +++ 2 files

[PATCH next v6 01/12] image: fit: Fix parameter name for hash algorithm

Fix inconsistent parameter naming of the hash algorithm. Signed-off-by: Chia-Wei Wang Fixes: 92055e138f2 ("image: Drop if/elseif hash selection in calculate_hash()") --- common/image-fit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/image-fit.c b/co

[PATCH next v6 02/12] aspeed: ast2600: Enlarge SRAM size

The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang --- arch/arm/include/asm/arch-aspeed/platform.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch

[PATCH next v5 11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific

Move CONFIG_EXTRA_ENV_SETTINGS to board-specific configuration headers. Signed-off-by: Chia-Wei Wang --- include/configs/aspeed-common.h | 9 - include/configs/evb_ast2500.h | 9 + include/configs/evb_ast2600.h | 9 + 3 files changed, 18 insertions(+), 9 deletions

[PATCH next v5 10/12] configs: ast2600-evb: Enable SPL FIT support

Enable SPL FIT image load and verification support. The HW accelerated SHA is also available with the newly added support of the HACE HW hash engine. The SPL thumb build is also enabled to keep the binary less than 64KB to fit into the Aspeed secure boot design. Signed-off-by: Chia-Wei Wang

[PATCH next v5 12/12] configs: ast2600: Boot kernel FIT in DRAM

. Therefore, we need to move the FIT image into DRAM before the booting. This patch update the CONFIG_BOOTCOMMAND to execute the pre-defined ENV variable which consists of FIT image copy to memory and booting. Signed-off-by: Chia-Wei Wang --- configs/evb-ast2600_defconfig | 2 +- include/configs

[PATCH next v5 04/12] crypto: aspeed: Add AST2600 HACE support

From: Johnny Huang Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang Signed-off-by: Chia-Wei Wang --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1

[PATCH next v5 03/12] clk: ast2600: Add YCLK control for HACE

From: Joel Stanley Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++-- drivers/clk/aspeed/clk_ast2600.c | 20 +++ 2 files

[PATCH next v5 09/12] ast2600: spl: Locate load buffer in DRAM space

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for spl_get_load_buffer() to allow generic SPL image loading code (e.g. FIT and Ymodem) to store data in DRAM. Signed-off-by: Chia-Wei Wang --- arch/arm/mach-aspeed/ast2600/spl.c | 9 + 1 file changed, 1 insertion(+), 8 deletions

[PATCH next v5 08/12] ARM: dts: ast2600: Add ACRY to device tree

Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 9 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index adb80a30ef

[PATCH next v5 07/12] crypto: aspeed: Add AST2600 ACRY support

ACRY is deisnged to accerlerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang --- drivers/crypto/aspeed/Kconfig | 10 ++ drivers/crypto/aspeed/Makefile | 1 + drivers/crypto/aspeed/aspeed_acry.c | 182 lib/rsa

[PATCH next v5 06/12] clk: ast2600: Add RSACLK control for ACRY

. Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 1 + drivers/clk/aspeed/clk_ast2600.c | 22 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch

[PATCH next v5 05/12] ARM: dts: ast2600: Add HACE to device tree

From: Joel Stanley Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 8 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b

[PATCH next v5 00/12] aspeed: Support secure boot chain with FIT image verification

next branch v3: - add SW work around for HACE HW DMA issue by resetting HACE - add reset control for HACE device tree node - sync all of the HACE error message to use debug() v2: - update commit authors Chia-Wei Wang (9): image: fit: Fix parameter name for hash algorithm aspeed: ast2600

[PATCH next v5 02/12] aspeed: ast2600: Enlarge SRAM size

The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang --- arch/arm/include/asm/arch-aspeed/platform.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch

[PATCH next v5 01/12] image: fit: Fix parameter name for hash algorithm

Fix inconsistent function parameter name of the hash algorithm. Signed-off-by: Chia-Wei Wang Fixes: 92055e138f2 ("image: Drop if/elseif hash selection in calculate_hash()") --- common/image-fit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/image-fit.

[PATCH next v4 02/11] clk: ast2600: Add YCLK control for HACE

From: Joel Stanley Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++-- drivers/clk/aspeed/clk_ast2600.c | 20 +++ 2 files

[PATCH next v4 09/11] configs: ast2600-evb: Enable SPL FIT support

Enable SPL FIT image load and verification support. The HW accelerated SHA is also available with the newly added support of the HACE HW hash engine. The SPL thumb build is also enabled to keep the binary less than 64KB to fit into the Aspeed secure boot design. Signed-off-by: Chia-Wei Wang

[PATCH next v4 10/11] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific

Move CONFIG_EXTRA_ENV_SETTINGS to board-specific configuration headers. Signed-off-by: Chia-Wei Wang --- include/configs/aspeed-common.h | 9 - include/configs/evb_ast2500.h | 9 + include/configs/evb_ast2600.h | 9 + 3 files changed, 18 insertions(+), 9 deletions

[PATCH next v4 11/11] configs: ast2600: Boot kernel FIT in DRAM

. Therefore, we need to move the FIT image into DRAM before the booting. This patch update the CONFIG_BOOTCOMMAND to execute the pre-defined ENV variable which consists of FIT image copy to memory and booting. Signed-off-by: Chia-Wei Wang --- configs/evb-ast2600_defconfig | 2 +- include/configs

[PATCH next v4 06/11] crypto: aspeed: Add AST2600 ACRY support

ACRY is deisnged to accerlerate ECC/RSA digital signature generation and verification. Signed-off-by: Chia-Wei Wang --- drivers/crypto/aspeed/Kconfig | 10 ++ drivers/crypto/aspeed/Makefile | 1 + drivers/crypto/aspeed/aspeed_acry.c | 182 lib/rsa

[PATCH next v4 07/11] ARM: dts: ast2600: Add ACRY to device tree

Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 9 + 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index adb80a30ef

[PATCH next v4 08/11] ast2600: spl: Locate load buffer in DRAM space

Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for spl_get_load_buffer() to allow generic SPL image loading code (e.g. FIT and Ymodem) to store data in DRAM. Signed-off-by: Chia-Wei Wang --- arch/arm/mach-aspeed/ast2600/spl.c | 9 + 1 file changed, 1 insertion(+), 8 deletions

[PATCH next v4 04/11] ARM: dts: ast2600: Add HACE to device tree

From: Joel Stanley Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 + arch/arm/dts/ast2600.dtsi| 8 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b

[PATCH next v4 05/11] clk: ast2600: Add RSACLK control for ACRY

. Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 1 + drivers/clk/aspeed/clk_ast2600.c | 22 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch

[PATCH next v4 03/11] crypto: aspeed: Add AST2600 HACE support

From: Johnny Huang Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Johnny Huang Signed-off-by: Chia-Wei Wang --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1

[PATCH next v4 00/11] aspeed: Support secure boot chain with FIT image verification

resetting HACE - add reset control for HACE device tree node - sync all of the HACE error message to use debug() v2: - update commit authors Chia-Wei Wang (8): aspeed: ast2600: Enlarge SRAM size clk: ast2600: Add RSACLK control for ACRY crypto: aspeed: Add AST2600 ACRY support ARM: dts

[PATCH next v4 01/11] aspeed: ast2600: Enlarge SRAM size

The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang --- arch/arm/include/asm/arch-aspeed/platform.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch

[PATCH next] lib: hash-checksum: Use DM_HASH if supported

Use DM_HASH to perform hashing operations if supported. Thus either SW or HW-assisted hashing could be leveraged. Signed-off-by: Chia-Wei Wang --- lib/hash-checksum.c | 37 + 1 file changed, 37 insertions(+) diff --git a/lib/hash-checksum.c b/lib/hash

[PATCH] ARM: dts: ast2600: Make WDT by default disabled

The WDT devices described in the general .dtsi file should be marked as "disabled" by default. A WDT should be then enabled in the board specific .dts file on demands. Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600.dtsi | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v2] Rename CONFIG_SPL_FIT_SHAxxx to CONFIG_SPL_SHAxxx

BLED(SHA384) && strcmp(algo, "sha384") == 0) ... else if (CONFIG_IS_ENABLED(SHA512) && strcmp(algo, "sha512") == 0) ... Signed-off-by: Chia-Wei Wang --- v2: - fix typo in the commit title common/spl/Kconfig | 8 1 file cha

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