normal binman builds to
EXT_DTB usecase as well.
Signed-off-by: Manorit Chawdhry
Reviewed-by: Aniket Limaye
---
Makefile | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index
e60bbb01a004c7801034a10e7f3fdd04f92f700d
On 08/04/25 18:29, Heiko Schocher wrote:
Hello Aniket,
On 10.03.25 11:36, Aniket Limaye wrote:
Remove __omap24_i2c_read/write() usage from omap_i2c_xfer() in favour of
the more flexible __omap24_i2c_xfer_msg().
Consequently, these are also no longer needed when DM_I2C is enabled.
New
Add a Kconfig option to disable sending Stop conditions between multiple
i2c_msgs within a single xfer. Enable this config by default for ARCH_K3
platforms.
Signed-off-by: Aniket Limaye
---
v2:
- CONFIG_I2C_REPEATED_START -> CONFIG_SYS_I2C_OMAP24XX_REPEATED_START
- Link to v1:
ht
timeout in
the absence of a stop condition (BB will be 1 until Stop is programmed)
Signed-off-by: Aniket Limaye
---
v2:
- fixup code formatting and comment blocks
- CONFIG_I2C_REPEATED_START -> CONFIG_SYS_I2C_OMAP24XX_REPEATED_START
- Link to v1:
https://lore.kernel.org/u-boot/20250304220546.86660
functions, with hardcoded addr=0 and alen=0 for each i2c_msg. Each of
these calls would program the registers always with a Stop bit set, not
allowing for a repeated start between i2c_msgs in the same xfer().
[0]: https://www.ti.com/lit/zip/spruj28 (TRM)
Signed-off-by: Aniket Limaye
---
v3:
- Fixup to
Remove unused piece of code under CONFIG_I2C_REPEATED_START which does
not have any Kconfig entry at all.
Signed-off-by: Aniket Limaye
---
drivers/i2c/omap24xx_i2c.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c
CONFIG_SYS_I2C_OMAP24XX_REPEATED_START
- Return right error codes and update debug prints to be driver specific
- patch formatting updates
- Link to v1:
https://lore.kernel.org/u-boot/20250304220546.866602-1-a-lim...@ti.com/
Aniket Limaye (4):
i2c: omap24xx_i2c: Remove unused CONFIG_I2C_REPEATED_START
i2c: omap24xx_i2c
functions, with hardcoded addr=0 and alen=0 for each i2c_msg. Each of
these calls would program the registers always with a Stop bit set, not
allowing for a repeated start between i2c_msgs in the same xfer().
[0]: https://www.ti.com/lit/zip/spruj28 (TRM)
Signed-off-by: Aniket Limaye
---
v2:
- Use
://lore.kernel.org/u-boot/20250304220546.866602-1-a-lim...@ti.com/
Aniket Limaye (4):
i2c: omap24xx_i2c: Remove unused CONFIG_I2C_REPEATED_START
i2c: omap24xx_i2c: Use new function __omap24_i2c_xfer_msg()
i2c: omap24xx_i2c: support CONFIG for repeated start in DM_I2C xfer
drivers: i2c
Add a Kconfig option to disable sending Stop conditions between multiple
i2c_msgs within a single xfer. Enable this config by default for ARCH_K3
platforms.
Signed-off-by: Aniket Limaye
---
v2:
- CONFIG_I2C_REPEATED_START -> CONFIG_SYS_I2C_OMAP24XX_REPEATED_START
- Link to v1:
ht
timeout in
the absence of a stop condition (BB will be 1 until Stop is programmed)
Signed-off-by: Aniket Limaye
---
v2:
- fixup code formatting and comment blocks
- CONFIG_I2C_REPEATED_START -> CONFIG_SYS_I2C_OMAP24XX_REPEATED_START
- Link to v1:
https://lore.kernel.org/u-boot/20250304220546.86660
Remove unused piece of code under CONFIG_I2C_REPEATED_START which does
not have any Kconfig entry at all.
Signed-off-by: Aniket Limaye
---
drivers/i2c/omap24xx_i2c.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c
On 06/03/25 11:24, Heiko Schocher wrote:
Hello Aniket,
On 04.03.25 23:04, Aniket Limaye wrote:
Repeated Start Condition (Sr) can be used to transfer multiple i2c msgs
without sending a Stop condition (P). So far, the driver default was to
always send a Stop condition after every i2c msg
Hello Tom, Heiko,
On 06/03/25 11:15, Heiko Schocher wrote:
Hello Tom, Aniket,
On 05.03.25 16:50, Tom Rini wrote:
On Wed, Mar 05, 2025 at 03:34:08AM +0530, Aniket Limaye wrote:
This series implements Repeated Start functionality for the DM_I2C xfer
API (omap_i2c_xfer())
First, split out the
Hello Heiko,
On 06/03/25 11:21, Heiko Schocher wrote:
Hello Aniket,
On 04.03.25 23:04, Aniket Limaye wrote:
Remove __omap24_i2c_read/write() usage from omap_i2c_xfer() in favour of
the more flexible __omap24_i2c_xfer_msg().
Consequently, these are also no longer needed when DM_I2C is enabled
absence of a stop condition (BB will be 1 until Stop is programmed)
Signed-off-by: Aniket Limaye
---
drivers/i2c/omap24xx_i2c.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 0d044121d27
Signed-off-by: Aniket Limaye
---
drivers/i2c/Kconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index cdae6825736..ade86a71fb0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -503,6 +503,15 @@ config SYS_I2C_OMAP24XX
functions, with hardcoded addr=0 and alen=0 for each i2c_msg. Each of
these calls would program the registers always with a Stop bit set, not
allowing for a repeated start between i2c_msgs in the same xfer().
[0]: https://www.ti.com/lit/zip/spruj28 (TRM)
Signed-off-by: Aniket Limaye
---
drivers/i2c
CONFIG_I2C_REPEATED_START from the legacy
implementation of the driver or define a new config
- Default enable it for K3 devices?
[0]:
https://github.com/torvalds/linux/blob/v6.14-rc5/drivers/i2c/busses/i2c-omap.c#L699
Aniket Limaye (3):
i2c: omap24xx_i2c: Use new function __omap24_i2c_xfer_msg
Hi Manorit,
On 19/11/24 11:42, Manorit Chawdhry wrote:
Hi Aniket,
On 06:02-20241119, Aniket Limaye wrote:
The default j7200 devicetree and k3_avs driver set 2GHz/1GHz frequency
for A72/MSMC clks and the OPP_NOM voltage.
J7200 SOCs may support OPP_LOW Operating Performance Point:
1GHz/500MHz
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz ope
From: Reid Tonking
Define new CONFIG_K3_OPP_LOW under arm/mach-k3/r5/Kconfig and add
default value to j7200_evm_r5_defconfig
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v4:
- Move Config definition to arch/arm/mach-k3/r5/Kconfig
- Link to v3:
https://lore.kernel.org/u-boot
voltage for VDD_CPU through
k3_avs_notify_freq() callback from clk_k3.
[0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html
Signed-off-by: Aniket Limaye
---
v4:
- Fixup patch styling problems
- In previous versions, fdt_fixup_a72ss_clock_frequency() assumed a
fixed order of
as described in the Datasheet [0]
The register offsets and fields are described in the TRM (5.2.6.1.5
WKUP_VTM_VD_OPPVID_j Register) [1].
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
[1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM)
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Lim
error out if
the efuse data was not valid.
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v4:
- Update function name to k3_avs_check_opp and update description
- Link to v3:
https://lore.kernel.org/u-boot/20241116071615.839623-4-a-lim...@ti.com/
v3:
- Fix voltage spelling in
].
Considering the above, define the MSMC clk in the a72 node.
[0]:
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v4:
- Fixup patch styling problems
- Link to v3:
https://lore.kernel.org/u
as described in the Datasheet [0]
The register offsets and fields are described in the TRM (5.2.6.1.5
WKUP_VTM_VD_OPPVID_j Register) [1].
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
[1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM)
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Lim
select OPP_LOW specs:
- Check if OPP_LOW AVS voltage read from efuse is valid.
- Update the clock frequencies in devicetree.
- Program the OPP_LOW AVS voltage for VDD_CPU.
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v3:
- Use more descriptive name for
out if
the efuse data was not valid.
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v3:
- Fix voltage spelling in k3_check_opp() function description. No
functional change
- Link to v2:
https://lore.kernel.org/u-boot/20241023130033.1826413-4-a-lim...@ti.com/
v2:
- Update to also
From: Reid Tonking
Define new CONFIG_K3_OPP_LOW under arm/mach-k3/Kconfig and add default
value to j7200_evm_r5_defconfig
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v3:
- Add Kconfig dependency on K3_AVS0
- Update commit msg to make it more clear
- Link to v2:
https
].
Considering the above, define the MSMC clk in the a72 node.
[0]:
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v3:
- Add msmc clock at the end to preserve current ordering of core and
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz ope
On 30/10/24 13:58, Manorit Chawdhry wrote:
Hi Neha, Aniket,
On 13:31-20241030, Manorit Chawdhry wrote:
Hi Aniket,
On 15:40-20241029, Manorit Chawdhry wrote:
Hi Aniket,
On 18:27-20241023, Aniket Limaye wrote:
From: Reid Tonking
The default j7200 devicetree and k3_avs driver set 2GHz
Hi Manorit,
On 30/10/24 13:31, Manorit Chawdhry wrote:
Hi Aniket,
On 15:40-20241029, Manorit Chawdhry wrote:
Hi Aniket,
On 18:27-20241023, Aniket Limaye wrote:
From: Reid Tonking
The default j7200 devicetree and k3_avs driver set 2GHz/1GHz frequency
for A72/MSMC clks and the OPP_NOM
].
Considering the above, define the MSMC clk in the a72 node.
[0]:
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v2:
- Update commit msg to justify location of msmc clk in DT
- Link to v1
From: Reid Tonking
Adds the default config for K3_OPP_LOW in J7200
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
arch/arm/mach-k3/Kconfig | 6 ++
configs/j7200_evm_r5_defconfig | 1 +
2 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm
out if
the efuse data was not valid.
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v2:
- Update to also handle invalid efuse voltage reading in
k3_avs_program_voltage() and reflect the same change in commit msg.
- Link to v1:
https://lore.kernel.org/u-boot
as described in the Datasheet [0]
The register offsets and fields are described in the TRM (5.2.6.1.5
WKUP_VTM_VD_OPPVID_j Register) [1].
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
[1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM)
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Lim
select OPP_LOW specs:
- Check if OPP_LOW AVS voltage read from efuse is valid.
- Update the clock frequencies in devicetree.
- Program the OPP_LOW AVS voltage for VDD_CPU.
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
v2:
- Fix indentation in fix_freq()
- Remove the efuse data
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz ope
On 23/10/24 12:17, Neha Malcom Francis wrote:
Hi Aniket
On 23/10/24 11:42, Aniket Limaye wrote:
On 17/10/24 16:00, Neha Malcom Francis wrote:
Hi Aniket
On 17/10/24 11:59, Aniket Limaye wrote:
From: Reid Tonking
Define the MSMC clk in the a72 node
The usage of MSMC and A72SS
On 17/10/24 16:00, Neha Malcom Francis wrote:
Hi Aniket
On 17/10/24 11:59, Aniket Limaye wrote:
From: Reid Tonking
Define the MSMC clk in the a72 node
The usage of MSMC and A72SS interchangeably in this series is confusing.
Could you expand on it in the cover letter why in J7200 this
On 17/10/24 23:24, Tom Rini wrote:
On Thu, Oct 17, 2024 at 11:59:13AM +0530, Aniket Limaye wrote:
From: Reid Tonking
This just provides some useful print outs and the proper config to
test the functionality. For J7200 boards that do not have efuse
burned in, the hardcoded 76 is needed
: Aniket Limaye
---
arch/arm/mach-k3/j721e/j721e_init.c | 9 +
configs/j7200_evm_r5_defconfig | 2 +-
drivers/misc/k3_avs.c | 4 +++-
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c
b/arch/arm/mach-k3/j721e/j721e_init.c
index
From: Reid Tonking
Adds the default config for K3_OPP_LOW in J7200
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
arch/arm/mach-k3/Kconfig | 6 ++
configs/j7200_evm_r5_defconfig | 1 +
2 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm
select OPP_LOW specs:
- Check if OPP_LOW AVS voltage read from efuse is valid.
- Update the clock frequencies in devicetree.
- Program the OPP_LOW AVS voltage for VDD_CPU.
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
arch/arm/mach-k3/j721e/j721e_init.c | 45
-off-by: Aniket Limaye
---
drivers/misc/k3_avs.c | 25 +
include/k3-avs.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
index 9d950d034a5..90cd9dfe7f9 100644
--- a/drivers/misc/k3_avs.c
+++ b/drivers/misc/k3_avs.c
as described in the Datasheet [0]
The register offsets and fields are described in the TRM (5.2.6.1.5
WKUP_VTM_VD_OPPVID_j Register) [1].
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
[1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM)
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Lim
From: Reid Tonking
Define the MSMC clk in the a72 node
Signed-off-by: Reid Tonking
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
AVS test logs (CONFIG_K3_OPP_LOW enabled and dummy efuse value):
https://gist.github.com/aniket-l/3bdb454d2416e1900dce795ce6090507
J7200 SOC supports OPP_LOW and OPP_NOM as two
drivers: misc: k3_avs: Extract MPU clk and dev ID from DT
arm: mach-k3: j721s2_init: Initialize AVS Class 0
arm: dts: j721s2: Add VTM node in R5
configs: j721s2_evm_r5_defconfig: Add AVS Configs
For the series,
Reviewed-by: Aniket Limaye
arch/arm/dts/k3-am62-r5-lp
From: Neha Malcom Francis
Add CONFIG_ESM_PMIC to enable PMIC initialization in J7200.
Signed-off-by: Neha Malcom Francis
Signed-off-by: Aniket Limaye
---
configs/j7200_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/j7200_evm_r5_defconfig b/configs
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 176cc0a0fbb..9c83a629504 100644
--- a/arch/arm/dts/k3-j7200-r5
From: Neha Malcom Francis
Add CONFIG_ESM_K3 to enable ESM initialization in J7200.
Signed-off-by: Neha Malcom Francis
Signed-off-by: Aniket Limaye
---
configs/j7200_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/j7200_evm_r5_defconfig b/configs
From: Gowtham Tammana
Hook buckb1 to vtm avs supply.
Signed-off-by: Gowtham Tammana
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5
To avoid whitespace diff, use tabs throughout the file for indent
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200
Add bootph-pre-ram property to the buck node in the pmic needed for
ESM error event handling.
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm
This series adds the required nodes in the devicetree, and enables the
configs for the ESM and PMIC.
Test Logs AVS and ESM:
https://gist.github.com/aniket-l/96b85a25733095b4fd87f48f730518bf
---
Aniket Limaye (2):
arm: dts: k3-j7200-r5: Add the pmic node in R5 dt
arm: dts: k3-j7200-r5: Fix
Move to using OF_UPSTREAM config and thus using the devicetree-rebasing
subtree.
Signed-off-by: Aniket Limaye
---
Boot logs:
https://gist.github.com/aniket-l/aab91bb12d2495c54da094fca49c369f
Changes in v2:
- Rebased to next
- Removed dependency on binman templating series [1] as per [2]
[1
Move to using OF_UPSTREAM config and thus using the devicetree-rebasing
subtree.
Signed-off-by: Aniket Limaye
---
arch/arm/dts/Makefile |1 -
.../k3-j7200-common-proc-board-u-boot.dtsi| 16 +-
arch/arm/dts/k3-j7200-common-proc-board.dts | 396 -
arch/arm
...@ti.com/
Boot logs:
https://gist.github.com/aniket-l/5ae460224307ed7bf47f20488e1d3457
Aniket Limaye (1):
arm: dts: k3-j7200: Move to OF_UPSTREAM
arch/arm/dts/Makefile |1 -
.../k3-j7200-common-proc-board-u-boot.dtsi| 16 +-
arch/arm/dts/k3-j7200-common-proc
Corrects the ti,sci property to point to dm_tifs node for proper
functioning of mcu_ringacc and mcu_udmap.
Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1")
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 8
1 file
Correcting the clock-frequency property of the mcu_timer0 node
Fixes: df73e791ce09 ("arm: dts: j7200: dts sync with Linux 6.6-rc1")
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
- Add the missing bootph-all property in the flash subnode for ospi
- Add the missing overrides for the ospi node in the r5 devicetree
Signed-off-by: Aniket Limaye
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 4
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 5 +
2
Add the necessary configs required for OSPI functionality.
Also update the ospi flash partition offsets as per the devicetree.
Signed-off-by: Aniket Limaye
---
configs/j7200_evm_a72_defconfig | 10 --
configs/j7200_evm_r5_defconfig | 9 +++--
2 files changed, 15 insertions(+), 4
7200-evm device.
- sf probe and update in u-boot prompt & successful OSPI boot logs [1]
[0]: https://gist.github.com/aniket-l/f487472baa47e819defc82e5f57b7860
[1]: https://gist.github.com/aniket-l/e5353c4511009d2ebf5f1743ebaab61a
Aniket Limaye (4):
configs: j7200_evm_*_defconfig: Enable OSPI
66 matches
Mail list logo
