Chee Hong Ang mailto:chee.hong@intel.com>> schrieb
am Mo., 17. Aug. 2020, 06:34:
Repost of the following patchs:
https://lists.denx.de/pipermail/u-boot/2020-March/402705.html
> If this is a repost, please send as such instead of sending as a new series
> v1.
Sorry, please ignore the repost
> On 8/11/20 10:01 AM, Chee Hong Ang wrote:
> > Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> > for booting up Cyclone5/Arria10.
> >
> > For Cyclone5 using NAND flash image layout for 128 KB memory blocks,
> > 'make u-boot-with-nand-spl.sfp' to generate spl/u-boot-nand-splx
> Hi,
>
> On 05/08/20 3:48 pm, Chee Hong Ang wrote:
> > If the QSPI clock is not set (read as 0), QSPI driver probe shall fail
> > and prevent further QSPI access.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > drivers/spi/cadence_qspi.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > d
> > -Original Message-
> > From: Ang, Chee Hong
> > Sent: Wednesday, August 5, 2020 5:54 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Simon Goldschmidt
> > ; Tom Rini ; See,
> > Chin Liang ; Tan, Ley Foon
> > ; Ang, Chee
> > From: Ang, Chee Hong
> > Sent: Friday, July 10, 2020 8:55 PM
> > To: u-boot@lists.denx.de
> > Cc: Marek Vasut ; Simon Goldschmidt
> > ; See, Chin Liang
> > ; Tan, Ley Foon ;
> > Ang, Chee Hong
> > Subject: [PATCH v1 3/4] clk: agilex: Handle
> On Fri, Apr 3, 2020 at 6:56 AM Ang, Chee Hong
> wrote:
> >
> > > On Thu, Apr 2, 2020 at 7:28 PM Ang, Chee Hong
> > >
> > > wrote:
> > > > > On Thu, Apr 02, 2020 at 12:55:14PM +0800, Bin Meng wrote:
> > > > > > On Thu,
> On Thu, Apr 2, 2020 at 7:28 PM Ang, Chee Hong
> wrote:
> > > On Thu, Apr 02, 2020 at 12:55:14PM +0800, Bin Meng wrote:
> > > > On Thu, Apr 2, 2020 at 1:55 AM Simon Glass wrote:
> > > > > On Wed, 1 Apr 2020 at 11:39, Andy Shevchenko
> > > wr
> On Thu, Apr 02, 2020 at 12:55:14PM +0800, Bin Meng wrote:
> > Hi Simon, Andy,
> >
> > On Thu, Apr 2, 2020 at 1:55 AM Simon Glass wrote:
> > >
> > > Hi Andy,
> > >
> > > On Wed, 1 Apr 2020 at 11:39, Andy Shevchenko
> wrote:
> > > >
> > > > On Wed, Apr 01, 2020 at 10:56:26AM -0600, Simon Glass wr
> On 4/2/20 4:34 AM, Simon Glass wrote:
> > Hi,
> >
> > On Tue, 31 Mar 2020 at 20:33, Ang, Chee Hong
> wrote:
> >>
> >>> Hi Marek,
> >>>
> >>> On Wed, 11 Mar 2020 at 05:55, Marek Vasut wrote:
> >>>>
> >&
Hi Marek/Simon,
Can you please help review and comment on this patchsets ?
> Any comment on this v5 patchsets ?
>
> > From: "Ang, Chee Hong"
> >
> > v5 changes:
> > This is another revision without the System Manager driver to handle
> > the secure/
> Hi Marek,
>
> On Wed, 11 Mar 2020 at 05:55, Marek Vasut wrote:
> >
> > On 3/11/20 12:50 PM, Simon Glass wrote:
> > > Hi,
> >
> > Hi,
> >
> > > On Mon, 9 Mar 2020 at 02:22, wrote:
> > >>
> > >> From: Chee Hong Ang
> > >>
> > >> This commit (82de42fa14682d408da935adfb0f935354c5008f) calls
> > >
Any comment on this v5 patchsets ?
> From: "Ang, Chee Hong"
>
> v5 changes:
> This is another revision without the System Manager driver to handle the
> secure/non-secure access. DW MAC and MMC drivers will make direct calls to
> the high-level API to ATF if it&#
> On 3/11/20 8:03 AM, Ang, Chee Hong wrote:
> >> On 3/11/20 7:35 AM, Ang, Chee Hong wrote:
> >> [...]
> >>
> >>>>>> Hmm, so you're just using misc_ops to still issue generic writes.
> >>>>>> From the discussion with Ma
> -Original Message-
> From: Simon Goldschmidt
> Sent: Wednesday, March 11, 2020 1:06 AM
> To: Ang, Chee Hong ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang ;
> Tan, Ley Foon ; Westergreen, Dalon
> ; Gong, Richard
> Subject: Re: [PATCH v4 14/21]
> On 3/11/20 7:35 AM, Ang, Chee Hong wrote:
> [...]
>
> >>>> Hmm, so you're just using misc_ops to still issue generic writes.
> >>>> From the discussion with Marek in the last version, I would have
> >>>> thought you wanted to c
> Am 10.03.2020 um 17:42 schrieb Ang, Chee Hong:
> >> -Original Message-
> >> From: Simon Goldschmidt
> >> Sent: Wednesday, March 11, 2020 12:17 AM
> >> To: Ang, Chee Hong
> >> Cc: u-boot@lists.denx.de; Marek Vasut ; See, Chin
>
> Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> > From: Chee Hong Ang
> >
> > Enable this misc driver model for 'altera_sysmgr' driver for socfpga
> > platforms.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/Kconfig | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff
> Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> > From: "Ang, Chee Hong"
> >
> > v4 changes:
> > [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager
> > - Add System Manager driver (UCLASS_MISC) to handle secure access for
&g
> -Original Message-
> From: Simon Goldschmidt
> Sent: Wednesday, March 11, 2020 12:17 AM
> To: Ang, Chee Hong
> Cc: u-boot@lists.denx.de; Marek Vasut ; See, Chin Liang
> ; Tan, Ley Foon ;
> Westergreen, Dalon ; Gong, Richard
>
> Subject: Re: [PATCH v4 11/2
> On 3/9/20 9:21 AM, chee.hong@intel.com wrote:
> > From: Chee Hong Ang
> >
> > This commit (82de42fa14682d408da935adfb0f935354c5008f) calls child's
> > ofdata_to_platdata() method before the parent is probed in dm core.
> > This has caused the driver no longer able to get the correct parent
>
Ang, Chee Hong mailto:chee.hong@intel.com>>
schrieb am Fr., 28. Feb. 2020, 03:53:
> > On 2/24/20 3:21 AM, Ang, Chee Hong wrote:
> > [...]
> >
> > >>>>> Currently, we have like 20+ secure registers allowed access by
> > >>>
> > On 2/24/20 3:21 AM, Ang, Chee Hong wrote:
> > [...]
> >
> > >>>>> Currently, we have like 20+ secure registers allowed access by
> > >>>>> drivers running in non-secure mode (U-Boot proper / Linux).
> > >>>>> I
> On 2/24/20 3:21 AM, Ang, Chee Hong wrote:
> [...]
>
> >>>>> Currently, we have like 20+ secure registers allowed access by
> >>>>> drivers running in non-secure mode (U-Boot proper / Linux).
> >>>>> I don't think we want to
Ang, Chee Hong mailto:chee.hong@intel.com>>
schrieb am Sa., 22. Feb. 2020, 06:30:
> From: Chee Hong Ang mailto:chee.hong@intel.com>>
>
> Allow clock manager driver to access the System Manager's Boot Scratch
> Register 0 in non-secure mode (EL2) on SoC 64bit
> > > On 2/22/20 11:05 AM, Ang, Chee Hong wrote:
> > > >>> From: Chee Hong Ang
> > > >>>
> > > >>> Allow reading external oscillator and FPGA clock's frequency
> > > >>> from System Manager's Boot Scratch
From: Ang, Chee Hong
Sent: Saturday, February 22, 2020 6:00 PM
To: Simon Goldschmidt
Cc: U-Boot Mailing List ; Marek Vasut ;
See, Chin Liang ; Tan, Ley Foon
; Westergreen, Dalon ;
Gong, Richard
Subject: RE: [PATCH v2 11/21] arm: socfpga: Secure register access for clock
manager (SoC 64bits
> > On 2/22/20 11:05 AM, Ang, Chee Hong wrote:
> > >>> From: Chee Hong Ang
> > >>>
> > >>> Allow reading external oscillator and FPGA clock's frequency from
> > >>> System Manager's Boot Scratch Register 1 and Boo
> On 2/21/20 7:15 PM, Ang, Chee Hong wrote:
> >> On 2/20/20 6:04 PM, Westergreen, Dalon wrote:
> >>
> >> Please fix your mailer, it makes your reply completely unreadable.
> >>
> >>> On Thu, 2020-02-20 at 17:44 +0100, Marek Vasut wrote:
&
> On 2/21/20 8:06 PM, Ang, Chee Hong wrote:
> >> On 2/21/20 7:01 PM, Ang, Chee Hong wrote:
> >>>> On 2/20/20 6:54 PM, Ang, Chee Hong wrote:
> >>>>>> On 2/20/20 3:02 AM, Ang, Chee Hong wrote:
> >>>>>> [...]
> >>>&
> On 2/22/20 11:05 AM, Ang, Chee Hong wrote:
> >>> From: Chee Hong Ang
> >>>
> >>> Allow reading external oscillator and FPGA clock's frequency from
> >>> System Manager's Boot Scratch Register 1 and Boot Scratch Register 2
> >>
> > From: Chee Hong Ang
> >
> > Allow reading external oscillator and FPGA clock's frequency from
> > System Manager's Boot Scratch Register 1 and Boot Scratch Register 2
> > in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/w
Ang, Chee Hong mailto:chee.hong@intel.com>>
schrieb am Sa., 22. Feb. 2020, 06:30:
> From: Chee Hong Ang mailto:chee.hong@intel.com>>
>
> Allow clock manager driver to access the System Manager's Boot Scratch
> Register 0 in non-secure mode (EL2) on SoC 64bit
> From: Chee Hong Ang
>
> Allow socfpga_bridges_reset() function in Reset Manager driver to access
> System Manager's register in non-secure mode (EL2).
>
> Signed-off-by: Chee Hong Ang
> ---
> arch/arm/mach-socfpga/reset_manager_s10.c | 31 ++--
> ---
> 1 file changed,
> From: Chee Hong Ang
>
> Allow MAC driver to access System Manager's EMAC control registers in non-
> secure mode.
>
> Signed-off-by: Chee Hong Ang
> ---
> drivers/net/dwmac_socfpga.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/dwmac_socfpga.c b/
> From: Chee Hong Ang
>
> Allow MMC driver to access System Manager's SDMMC control register in non-
> secure mode (EL2).
>
> Signed-off-by: Chee Hong Ang
> ---
> drivers/mmc/socfpga_dw_mmc.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/socfpga_d
> From: Chee Hong Ang
>
> Allow reading external oscillator and FPGA clock's frequency from System
> Manager's Boot Scratch Register 1 and Boot Scratch Register 2 in non-secure
> mode (EL2) on SoC 64bits platform.
>
> Signed-off-by: Chee Hong Ang
> ---
> arch/arm/mach-socfpga/wrap_pll_config_s
> From: Chee Hong Ang
>
> Allow access to System Manager's EMAC control register from non-secure mode
> during PHY mode setup.
>
> Signed-off-by: Chee Hong Ang
> ---
> arch/arm/mach-socfpga/misc_s10.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mac
> From: Chee Hong Ang
>
> Allow clock manager driver to access the System Manager's Boot Scratch
> Register 0 in non-secure mode (EL2) on SoC 64bits platform.
>
> Signed-off-by: Chee Hong Ang
> ---
> arch/arm/mach-socfpga/clock_manager_agilex.c | 5 +++--
> arch/arm/mach-socfpga/clock_manager_
> On 2/21/20 7:01 PM, Ang, Chee Hong wrote:
> >> On 2/20/20 6:54 PM, Ang, Chee Hong wrote:
> >>>> On 2/20/20 3:02 AM, Ang, Chee Hong wrote:
> >>>> [...]
> >>>>>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL
> > On 2/20/20 8:05 PM, Ang, Chee Hong wrote:
> > >> On 2/20/20 3:27 AM, Ang, Chee Hong wrote:
> > >>>> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> > >>>> [...]
> > >>>>> diff --git a/arch/arm/mach-socfpga/lowl
> On 2/20/20 8:05 PM, Ang, Chee Hong wrote:
> >> On 2/20/20 3:27 AM, Ang, Chee Hong wrote:
> >>>> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> >>>> [...]
> >>>>> diff --git a/arch/arm/mach-socfpga/lowlevel_init.S
> >>>
> On 2/20/20 6:04 PM, Westergreen, Dalon wrote:
>
> Please fix your mailer, it makes your reply completely unreadable.
>
> > On Thu, 2020-02-20 at 17:44 +0100, Marek Vasut wrote:
> >
> > On 2/20/20 3:12 AM, Ang, Chee Hong wrote:
> >
> > On 2/19/20 1:25 P
> On 2/20/20 6:54 PM, Ang, Chee Hong wrote:
> >> On 2/20/20 3:02 AM, Ang, Chee Hong wrote:
> >> [...]
> >>>>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> >>>>> +u32 socfpga_secure_reg_read32(phys_addr_t reg_add
> On 2/20/20 3:27 AM, Ang, Chee Hong wrote:
> >> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> >> [...]
> >>> diff --git a/arch/arm/mach-socfpga/lowlevel_init.S
> >>> b/arch/arm/mach-socfpga/lowlevel_init.S
> >>> new file mod
> -Original Message-
> From: Marek Vasut
> Sent: Friday, February 21, 2020 12:48 AM
> To: Ang, Chee Hong ; u-boot@lists.denx.de
> Cc: Simon Goldschmidt ; See, Chin Liang
> ; Tan, Ley Foon ;
> Westergreen, Dalon ; Gong, Richard
> ; Tom Rini ; Michal Simek
>
> On 2/20/20 3:02 AM, Ang, Chee Hong wrote:
> [...]
> >>> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> >>> +u32 socfpga_secure_reg_read32(phys_addr_t reg_addr); void
> >>> +socfpga_secure_reg_write32(u32 val, phys_addr_t
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> > From: Chee Hong Ang
> >
> > Allow clock manager driver to access the System Manager's Boot Scratch
> > Register 0 in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/clock
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> [...]
> > diff --git a/arch/arm/mach-socfpga/lowlevel_init.S
> > b/arch/arm/mach-socfpga/lowlevel_init.S
> > new file mode 100644
> > index 000..68053a0
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/lowlevel_init.S
>
> This should be s
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> > From: Chee Hong Ang
> >
> > SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The
> > new boot flow with ATF support is as follow:
> >
> > SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
> >
> > Signed-off-by: Chee Hong Ang
>
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> > From: Chee Hong Ang
> >
> > CONFIG_OF_EMBED was primarily enabled to support the agilex spl hex
> > file requirements. Since this option now produces a warning during
> > build, and the spl hex can be created using alternate methods,
> > CO
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> > From: Chee Hong Ang
> >
> > These secure register access functions allow U-Boot proper running at
> > EL2 (non-secure) to access System Manager's secure registers by
> > calling the ATF's PSCI runtime services (EL3/secure). If these helper
>
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> [...]
> > +++ b/include/linux/intel-smc.h
> > @@ -0,0 +1,374 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017-2018, Intel Corporation
>
> 2020 ?
This file is new in U-Boot but it already exists in Linux kernel
> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
> [...]
>
> > +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) int
> > +invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int
> > +ret_len) {
> > + int i;
> > + struct pt_regs regs;
> > +
> > + memset(®s, 0, sizeof(re
> Am 03.12.2019 um 19:31 schrieb Ang, Chee Hong:
> >> On Tue, Dec 3, 2019 at 3:45 PM Ang, Chee Hong
> >>
> >> wrote:
> >>>
> >>>> On Tue, Dec 3, 2019 at 2:37 AM Ang, Chee Hong
> >>>>
> >>>> wrote:
> >>
> Am 02.12.2019 um 11:25 schrieb chee.hong@intel.com:
> > From: "Ang, Chee Hong"
> >
> > New U-boot flow with ARM Trusted Firmware (ATF) support:
> > SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
> >
> > SPL loads t
> On Tue, Dec 3, 2019 at 3:45 PM Ang, Chee Hong
> wrote:
> >
> > > On Tue, Dec 3, 2019 at 2:37 AM Ang, Chee Hong
> > >
> > > wrote:
> > > >
> > > > > Am 02.12.2019 um 17:10 schrieb Ang, Chee Hong:
> > > > >
> On Tue, Dec 3, 2019 at 2:37 AM Ang, Chee Hong
> wrote:
> >
> > > Am 02.12.2019 um 17:10 schrieb Ang, Chee Hong:
> > > >> On Mon, Dec 2, 2019 at 4:18 PM Ang, Chee Hong
> > > >>
> > > >> wrote:
> > > >>>
&
> Am 02.12.2019 um 17:10 schrieb Ang, Chee Hong:
> >> On Mon, Dec 2, 2019 at 4:18 PM Ang, Chee Hong
> >>
> >> wrote:
> >>>
> >>>> On Mon, Dec 2, 2019 at 3:08 PM Ang, Chee Hong
> >>>>
> >>>> wrote:
> On Mon, Dec 2, 2019 at 4:18 PM Ang, Chee Hong
> wrote:
> >
> > > On Mon, Dec 2, 2019 at 3:08 PM Ang, Chee Hong
> > >
> > > wrote:
> > > >
> > > > > On Mon, Dec 2, 2019 at 2:38 PM Ang, Chee Hong
> > > > >
&g
> On Mon, Dec 2, 2019 at 3:08 PM Ang, Chee Hong
> wrote:
> >
> > > On Mon, Dec 2, 2019 at 2:38 PM Ang, Chee Hong
> > >
> > > wrote:
> > > >
> > > > > On Mon, Dec 2, 2019 at 11:25 AM wrote:
> > > > > >
> >
> > On Mon, Dec 2, 2019 at 2:38 PM Ang, Chee Hong
> >
> > wrote:
> > >
> > > > On Mon, Dec 2, 2019 at 11:25 AM wrote:
> > > > >
> > > > > From: "Ang, Chee Hong"
> > > > >
> > > > > Ne
> On Mon, Dec 2, 2019 at 2:38 PM Ang, Chee Hong
> wrote:
> >
> > > On Mon, Dec 2, 2019 at 11:25 AM wrote:
> > > >
> > > > From: "Ang, Chee Hong"
> > > >
> > > > New U-boot flow with ARM Trusted Firmware (ATF) su
> On Mon, Dec 2, 2019 at 11:25 AM wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > New U-boot flow with ARM Trusted Firmware (ATF) support:
> > SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
>
> Adding support for ATF mea
On Thu, 2019-05-09 at 08:59 +0200, Marek Vasut wrote:
> On 5/9/19 7:52 AM, Ang, Chee Hong wrote:
> >
> > On Mon, 2019-05-06 at 22:20 -0700, chee.hong@intel.com wrote:
> > >
> > > From: "Ang, Chee Hong"
> > >
> > > Add "S
On Mon, 2019-05-06 at 22:20 -0700, chee.hong@intel.com wrote:
> From: "Ang, Chee Hong"
>
> Add "SYTEM_RESET" (cold reset) and "CPU_ON" (SMP) PSCI support
> for booting Linux on Stratix 10 platform.
>
> Ang, Chee Hong (3):
> ARM: s
On Tue, 2019-05-07 at 16:39 +0200, Marek Vasut wrote:
> On 5/7/19 4:08 PM, Ang, Chee Hong wrote:
> >
> > On Tue, 2019-05-07 at 15:03 +0200, Marek Vasut wrote:
> > >
> > > On 5/7/19 7:07 AM, chee.hong@intel.com wrote:
> > > >
> > > >
On Tue, 2019-05-07 at 15:03 +0200, Marek Vasut wrote:
> On 5/7/19 7:07 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Notify Secure Device Manager (SDM) on the stage of HPS code
> > execution.
> > In general, there ar
On Fri, 2019-05-03 at 21:31 +0200, Marek Vasut wrote:
> On 5/3/19 7:56 PM, Ang, Chee Hong wrote:
> >
> > On Fri, 2019-05-03 at 19:04 +0200, Marek Vasut wrote:
> > >
> > > On 5/3/19 5:53 PM, Ang, Chee Hong wrote:
> > > >
> > > >
>
On Fri, 2019-05-03 at 19:04 +0200, Marek Vasut wrote:
> On 5/3/19 5:53 PM, Ang, Chee Hong wrote:
> >
> > On Fri, 2019-05-03 at 11:55 +0200, Marek Vasut wrote:
> > >
> > > On 5/3/19 10:18 AM, chee.hong@intel.com wrote:
> > > >
> > > >
On Fri, 2019-05-03 at 11:55 +0200, Marek Vasut wrote:
> On 5/3/19 10:18 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> Commit message is missing -- why do you need to enable the DMA330 ?
>
> Don't you have a reset driver, like A10
On Wed, 2019-03-13 at 12:01 -0400, Tom Rini wrote:
> On Wed, Mar 13, 2019 at 08:10:31AM +0000, Ang, Chee Hong wrote:
> >
> > On Mon, 2019-03-11 at 15:48 -0400, Tom Rini wrote:
> > >
> > > On Mon, Mar 11, 2019 at 03:27:52PM +, Ang, Chee Hong wrote:
> > &
On Mon, 2019-04-08 at 07:27 +, lars.povl...@microchip.com wrote:
> >
> > From: Ang, Chee Hong
> > Sent: Monday, April 8, 2019 05:10
> > To: Lars Povlsen - M31675 ;
> > tr...@konsulko.com; u-boot@lists.denx.de; macro.wav...@gmail.com;
> > albert.
On Thu, 2019-04-04 at 14:38 +0200, Lars Povlsen wrote:
> This fixes relaction isses with the PSCI_TABLE entries in
> the psci_32_table and psci_64_table.
>
> When using 32-bit adress pointers relocation was not being applied to
> the tables, causing PSCI handlers to point to the un-relocated code
On Mon, 2019-03-11 at 15:48 -0400, Tom Rini wrote:
> On Mon, Mar 11, 2019 at 03:27:52PM +0000, Ang, Chee Hong wrote:
> >
> > On Fri, 2019-03-08 at 13:09 -0500, Tom Rini wrote:
> > >
> > > On Tue, Feb 12, 2019 at 12:27:01AM -0800, ch
On Fri, 2019-03-08 at 13:09 -0500, Tom Rini wrote:
> On Tue, Feb 12, 2019 at 12:27:01AM -0800, chee.hong@intel.com
> wrote:
>
> >
> > From: "Ang, Chee Hong"
> >
> > Currently u-boot only support standard PSCI functions for power
> > manageme
On Tue, 2019-02-12 at 00:27 -0800, chee.hong@intel.com wrote:
> From: "Ang, Chee Hong"
Hi Tom/Albert,
Any comment on this patch ?
Best Regards,
Ang
>
> Currently u-boot only support standard PSCI functions for power
> management
> and lack of convenient met
On Fri, 2019-02-22 at 17:02 +0100, Marek Vasut wrote:
> On 2/22/19 4:19 PM, Ang, Chee Hong wrote:
> >
> > On Thu, 2019-02-21 at 11:06 +0100, Marek Vasut wrote:
> > >
> > > On 2/20/19 2:57 PM, Ang, Chee Hong wrote:
> > > >
> > > >
>
On Thu, 2019-02-21 at 11:06 +0100, Marek Vasut wrote:
> On 2/20/19 2:57 PM, Ang, Chee Hong wrote:
> >
> > On Mon, 2019-02-18 at 21:38 +0100, Marek Vasut wrote:
> > >
> > > On 2/18/19 3:51 PM, Ang, Chee Hong wrote:
> > > >
> > > >
>
On Mon, 2019-02-18 at 21:38 +0100, Marek Vasut wrote:
> On 2/18/19 3:51 PM, Ang, Chee Hong wrote:
> >
> > On Mon, 2019-02-18 at 12:57 +0100, Marek Vasut wrote:
> > >
> > > On 2/18/19 5:16 AM, chee.hong@intel.com wrote:
> > >
On Mon, 2019-02-18 at 12:57 +0100, Marek Vasut wrote:
> On 2/18/19 5:16 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > 'SET_BLOCKLEN' may occasionally fail on first attempt.
> Why ?
This is part of the workaround of m
Hi Tom,
Any comments on this patch ?
Best Regards,
Ang
On Tue, 2019-02-12 at 00:27 -0800, chee.hong@intel.com wrote:
> From: "Ang, Chee Hong"
>
> Currently u-boot only support standard PSCI functions for power
> management
> and lack of convenient met
On Wed, 2018-12-19 at 09:41 +0100, Marek Vasut wrote:
> On 12/19/2018 05:55 AM, Ang, Chee Hong wrote:
> >
> > On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote:
> > >
> > > On 12/18/2018 09:54 AM, chee.hong@intel.com wrote:
> > >
On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote:
> On 12/18/2018 09:54 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Enable Stratix10 FPGA reconfiguration support in defconfig.
> >
> > Si
On Tue, 2018-12-18 at 18:47 +0100, Marek Vasut wrote:
> On 12/18/2018 09:54 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Summary of v6 changes:
> > - Patch 1/4 and 4/4 are unchanged
> > - Patch 2/4:
> > -
On Thu, 2018-11-29 at 12:28 +0100, Marek Vasut wrote:
> On 11/29/2018 10:40 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Enable 'fpga' command in u-boot. User will be able to use the FPGA
> > command to program t
On Thu, 2018-11-29 at 12:25 +0100, Marek Vasut wrote:
> On 11/29/2018 10:40 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Summary of v5 changes:
> > - Patch 1/4, 2/4 and 4/4 are unchanged
> > - Patch 3/4:
> >
On Mon, 2018-11-19 at 14:12 +0100, Marek Vasut wrote:
> On 11/19/2018 10:57 AM, Simon Goldschmidt wrote:
> >
> > On Mon, Nov 19, 2018 at 10:46 AM wrote:
> > >
> > >
> > > From: "Ang, Chee Hong"
> > >
> > > Enable 'fpg
On Wed, 2018-11-14 at 12:52 +0100, Marek Vasut wrote:
> On 11/14/2018 08:09 AM, Ang, Chee Hong wrote:
> >
> > On Thu, 2018-10-11 at 10:03 +, Marek Vasut wrote:
> > >
> > > On 10/11/2018 08:21 AM, Ang, Chee Hong wrote:
> > > >
> > > >
On Thu, 2018-10-11 at 10:03 +, Marek Vasut wrote:
> On 10/11/2018 08:21 AM, Ang, Chee Hong wrote:
> >
> > On Wed, 2018-10-10 at 12:27 +0200, Marek Vasut wrote:
> > >
> > > On 10/10/2018 07:30 AM, Ang, Chee Hong wrote:
> > > >
> > > >
On Wed, 2018-10-10 at 12:27 +0200, Marek Vasut wrote:
> On 10/10/2018 07:30 AM, Ang, Chee Hong wrote:
> >
> > On Tue, 2018-10-09 at 14:48 +0200, Marek Vasut wrote:
> > >
> > > On 10/09/2018 05:03 AM, Ang, Chee Hong wrote:
> > > >
> > > >
On Tue, 2018-10-09 at 14:48 +0200, Marek Vasut wrote:
> On 10/09/2018 05:03 AM, Ang, Chee Hong wrote:
> >
> > On Mon, 2018-10-08 at 22:32 +0200, Marek Vasut wrote:
> > >
> > > On 10/08/2018 05:10 PM, Ang, Chee Hong wrote:
> > > >
> > > >
On Mon, 2018-10-08 at 22:32 +0200, Marek Vasut wrote:
> On 10/08/2018 05:10 PM, Ang, Chee Hong wrote:
> >
> > On Mon, 2018-10-08 at 11:57 +0200, Marek Vasut wrote:
> > >
> > > On 10/08/2018 11:48 AM, chee.hong@intel.com wrote:
> > >
On Mon, 2018-10-08 at 11:57 +0200, Marek Vasut wrote:
> On 10/08/2018 11:48 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Enable 'fpga' command in u-boot. User will be able to use the fpga
> > command to program t
On Thu, 2018-09-27 at 22:39 +0200, Marek Vasut wrote:
> On 09/27/2018 08:37 AM, Ang, Chee Hong wrote:
> >
> > On Thu, 2018-09-27 at 08:21 +0200, Marek Vasut wrote:
> > >
> > > On 09/27/2018 07:08 AM, Ang, Chee Hong wrote:
> > > >
> > > >
On Thu, 2018-09-27 at 08:21 +0200, Marek Vasut wrote:
> On 09/27/2018 07:08 AM, Ang, Chee Hong wrote:
> >
> > On Wed, 2018-09-26 at 16:53 +0200, Marek Vasut wrote:
> > >
> > > On 09/26/2018 11:03 AM, chee.hong@intel.com wrote:
> > >
On Wed, 2018-09-26 at 16:53 +0200, Marek Vasut wrote:
> On 09/26/2018 11:03 AM, chee.hong@intel.com wrote:
> >
> > From: "Ang, Chee Hong"
> >
> > Add a generic mailbox API for FPGA reconfig status which can be
> > called by others. This new functi
On Fri, 2018-04-27 at 09:08 +0200, Marek Vasut wrote:
> On 04/27/2018 07:51 AM, Ang, Chee Hong wrote:
> [...]
>
> >
> > >
> > > >
> > > > >
> > > > > >
> > > > > > + /* Check for any error
On Fri, 2018-04-27 at 09:08 +0200, Marek Vasut wrote:
> On 04/27/2018 07:31 AM, Ang, Chee Hong wrote:
> >
> > On Thu, 2018-04-26 at 14:38 +0200, Marek Vasut wrote:
> > >
> > > On 04/26/2018 08:15 AM, Ang, Chee Hong wrote:
> > > >
> > > >
On Thu, 2018-04-26 at 14:37 +0200, Marek Vasut wrote:
> On 04/26/2018 08:12 AM, Ang, Chee Hong wrote:
> >
> > On Fri, 2018-04-20 at 05:41 +0200, Marek Vasut wrote:
> > >
> > > On 04/20/2018 05:26 AM, chee.hong@intel.com wrote:
> > &g
On Thu, 2018-04-26 at 14:38 +0200, Marek Vasut wrote:
> On 04/26/2018 08:15 AM, Ang, Chee Hong wrote:
> >
> > On Fri, 2018-04-20 at 05:42 +0200, Marek Vasut wrote:
> > >
> > > On 04/20/2018 05:26 AM, chee.hong@intel.com wrote:
> > &g
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