On 4/15/25 17:04, Martin Kaistra wrote:
If the MII interface is used, the PHY is the clock master, thus don't
set the clock rate. On Zynq-7000, this will prevent the following
error:
zynq_gem ethernet@e000b000: failed to set tx clock rate 2500
Signed-off-by: Martin Kaistra
---
drive
On 5/22/25 08:07, Frantisek Bohacek wrote:
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.
This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
Hi Nishanth,
On 5/22/2025 9:18 PM, Nishanth Menon wrote:
On 08:45-20250522, Tom Rini wrote:
On Thu, May 22, 2025 at 12:48:28PM +0530, Beleswar Padhi wrote:
Previously, MCU R5F runs in lockstep mode. Enable split-mode on MCU R5F
as the support to shut down core1 and use it for loading other
Hi Tom,
On 5/22/2025 8:15 PM, Tom Rini wrote:
On Thu, May 22, 2025 at 12:48:28PM +0530, Beleswar Padhi wrote:
Previously, MCU R5F runs in lockstep mode. Enable split-mode on MCU R5F
as the support to shut down core1 and use it for loading other firmware,
while DM runs on core0, has been added.
Am 22. Mai 2025 03:17:45 MESZ schrieb "Ying-Chun Liu (PaulLiu)"
:
>From: "Ying-Chun Liu (PaulLiu)"
>
>Add EFI_SYSTEM_TABLE_POINTER structure for remote debugger to locate
>the address of EFI_SYSTEM_TABLE.
>
>This feature is described in UEFI SPEC version 2.10. Section 18.4.2.
>The implementation
Use lbaint_t for blknr to avoid overflow in ext4fs_read_file().
Background:
blknr (block number) used in ext4fs_read_file() could be increased to a
very large value and causes a wrap around at 32 bit signed integer max,
thus becomes negative. This results in an out-of-normal range for sector
numb
On Fri, May 23, 2025 at 12:07:06AM +0200, Casey Connolly wrote:
>
>
> On 5/22/25 21:51, Tom Rini wrote:
> > On Thu, May 22, 2025 at 10:39:38PM +0200, Casey Connolly wrote:
> >
> > > With several new Qualcomm platforms appearing on the mailing list, all
> > > of which build U-Boot as an ELF, sign
On Wed, 07 May 2025 13:23:42 +0100, Ben Dooks wrote:
> Add CONFIG_BOARD_INIT to specifu if the board_init() needs calling
> during initcall phase, and default it to 'y' for the relevant
> architectures which probably need it.
>
> This allows anyone with a board that doesn't need it to just remove
On Thu, 08 May 2025 19:37:24 +, Aristo Chen wrote:
> When decompressing GZIP-compressed image parts via the `imxtract` command,
> explicitly handle the `Z_BUF_ERROR` return value from `gunzip()` to provide
> a clearer diagnostic. This error typically indicates that the destination
> buffer is
On Tue, 06 May 2025 08:11:45 -0500, Bryan Brattlof wrote:
> TI's Foundational Security (TIFS), Device Management (DM) and Device
> Management and Security Control (DMSC) firmware are required for a
> successful boot. Remove the 'optional' flag so binman will emit an error
> if these firmware compo
On Tue, 06 May 2025 16:12:20 +0800, Weijie Gao wrote:
> Starting from commit ac30d90f336 (clk: Ensure the parent clocks are enabled
> while reparenting), MediaTek filogic platforms will crash on booting when
> initializing mmc devices.
>
> The root cause is that to simplify the code, we reused th
On Tue, 06 May 2025 09:08:59 +0200, Emanuele Ghidoli wrote:
> Several Kconfig options are enabled but unused or unnecessary for our
> use case. These include features such as SPL FAT support, YMODEM, and
> USB keyboard. Some R5-specific configurations are not used at all,
> as U-Boot proper is not
On Thu, 08 May 2025 17:15:42 +0200, Wadim Egorov wrote:
> Add fit_addr_r to the environment to allow us to boot from a FIT image.
>
>
Applied to u-boot/next, thanks!
[1/7] board: phytec: phycore_am62x: Update environment for fitboot
commit: fdd2af2c13848dbec1210a3361c667476c328263
[2/7]
On 5/22/25 21:51, Tom Rini wrote:
On Thu, May 22, 2025 at 10:39:38PM +0200, Casey Connolly wrote:
With several new Qualcomm platforms appearing on the mailing list, all
of which build U-Boot as an ELF, sign it, and then flash it to some
partition on the board, we're getting a lot of defconfi
From: Jean-Marie Verdun
Add support for the Wiznet W5500 spi to ethernet controller
Signed-off-by: Jean-Marie Verdun
---
drivers/net/Kconfig | 9 +
drivers/net/Makefile | 1 +
drivers/net/w5500.c | 610 +++
3 files changed, 620 insertions(+)
creat
On Thu, May 22, 2025 at 10:39:38PM +0200, Casey Connolly wrote:
> With several new Qualcomm platforms appearing on the mailing list, all
> of which build U-Boot as an ELF, sign it, and then flash it to some
> partition on the board, we're getting a lot of defconfigs which just
> contain a debug UA
Update the build docs to describe building the u-boot.mbn target
explicitly for some boards. Additionally add a new "signing" page to
describe the purpose of mkmbn and the MBN format.
Signed-off-by: Casey Connolly
---
doc/board/qualcomm/index.rst | 1 +
doc/board/qualcomm/rb3gen2.rst | 27 +++
Remove qcs9100_defconfig since it is now identical to qcom_defconfig.
Additionally remove the load address and REMAKE_ELF from other Qualcomm
defconfigs.
For these platforms you should explicitly build the u-boot.mbn target
which will have the correct load address and Qualcomm MBN signatures.
Sig
The QCM6490 and QCS9100 targets always enable debug UART, but this is
not really optimal for typical users.
Move these debug UART options to config fragments so that they aren't
enabled by default.
Signed-off-by: Casey Connolly
---
board/qualcomm/debug-qcm6490.config | 5 +
board/qualcomm/d
Wrap the new mkmbn tool so that the signed U-Boot MBN file is a
standard build target.
$ make DEVICE_TREE=qcom/qcs6490-rb3gen2 u-boot.mbn
Signed-off-by: Casey Connolly
---
Makefile | 3 +++
arch/arm/mach-snapdragon/Makefile | 8
2 files changed, 11 insertions(+
This is a fork of qtestsign[1] with modifications to integrate with the
U-Boot build system.
New Qualcomm dev boards flash U-Boot to the "uefi" partition, the format
is a standard ELF file with custom program headers containing Qualcomm
signatures, hashes and other metadata.
Since different board
+
tools/qcom/mkmbn/hashseg.py | 308
tools/qcom/mkmbn/mkmbn.py | 99
15 files changed, 876 insertions(+), 55 deletions(-)
---
base-commit: 8f85a7345ed5df70a155f0630da72970eb01d87a
change-id: 20250522-b4-qcom-tooling-improvements-ab40585b11a1
Casey Connolly
On Thu, May 22, 2025 at 9:48 AM wrote:
>
> On 22/05/2025 15:09, Eoin Dickson wrote:
> > From: Eoin Dickson
> >
> > This series add SD card support for the Beagle-V-Fire. The Beagle-V-Fire
> > uses the
> > Microchip coreqspi xfer function and a gpio chip select, so this series
> > adds gpio
> >
On Thu, 08 May 2025 13:57:25 +0200, Christoph Niedermaier wrote:
> The formatting with %pa / %pap behaves like %x, which results in an
> incorrect value being output. To improve this, a new fine-tuning
> Kconfig SPL_USE_TINY_PRINTF_POINTER_SUPPORT for pointer formatting
> has been added. If it is
On Thu, 08 May 2025 19:00:28 +, Johannes Krottmayer wrote:
> Since GNU binutils version 2.44, assembly functions must include
> the assembler directive .type name, %function. If not a call to
> these functions fails with the error message 'Unknown destination
> type (ARM/Thumb)' and the error
From: Jean-Marie Verdun
v5
Remove of_to_plat init
Remove unused cmd variable from probe
Remove socket open command from hw mac setup code
Remove read back mac address command from hw mac setup code
Improve comment about RX_RSR register usage
Check error code of spi_write calls
Check error code fr
On Wed, May 07, 2025 at 02:12:42PM +0200, Rasmus Villemoes wrote:
> While looking through list.h, I saw that the regular list_* helpers
> (and one of the hlist_* ones) still contain the prefetch() that was
> removed in linux 14 years ago. It doesn't do anything, but makes the
> macros harder to re
On Mon, May 12, 2025 at 09:39:31AM -0700, Max Filippov wrote:
> Enable DM_SERIAL for the xtensa architecture and update xtfpga_defconfig
>
> Signed-off-by: Max Filippov
> ---
> arch/Kconfig | 1 +
> configs/xtfpga_defconfig | 6 +++---
> 2 files changed, 4 insertions(+), 3 deletions
On Thu, May 22, 2025 at 12:28:18PM +0100, Conor Dooley wrote:
> On Wed, May 21, 2025 at 12:39:50PM -0600, Tom Rini wrote:
> > On Wed, 21 May 2025 17:50:03 +0800, Leo Liang wrote:
> >
> > > The following changes since commit
> > > a3e09b24ffd4429909604f1b28455b44306edbaa:
> > >
> > > Merge tag
There are common MMC args for TI plats in include/environment/ti/mmc.env.
Since we already include this, there is no need to redefine these
MMC vars. Use the defaults.
This seems like something that could have been done while refactoring
these vars in the first place as it happened after this AM62
On Mon, May 12, 2025 at 12:31:58PM +0530, Sumit Garg wrote:
> On Fri, May 09, 2025 at 04:54:43PM +0200, Stephan Gerhold wrote:
> > On Fri, May 09, 2025 at 12:45:20PM +0200, Casey Connolly wrote:
> > > On 5/8/25 12:32, Sumit Garg wrote:
> > > > From: Sumit Garg
> > > >
> > > > When debug serial po
On Thu, 22 May 2025 10:03:19 -0300, Fabio Estevam wrote:
> Please pull from u-boot-imx/master, thanks.
>
> The following changes since commit a3e09b24ffd4429909604f1b28455b44306edbaa:
>
> Merge tag 'mmc-2025-05-20' of
> https://source.denx.de/u-boot/custodians/u-boot-mmc (2025-05-20 08:35:31
On Wed, May 21, 2025 at 8:09 AM Fabio Estevam wrote:
>
> From: Olaf Baehring
>
> In rare cases U-Boot returns an error message when intantiating the RNG
> of the CAAM device:
> “SEC0: RNG4 SH0 instantiation failed with error 0x”
> This means, that even when the CAAM device reports a fin
On Thu, May 22, 2025 at 11:36:47PM +0800, Leo Liang wrote:
> On Thu, May 22, 2025 at 08:45:59AM -0600, Tom Rini wrote:
> > On Thu, May 22, 2025 at 12:28:18PM +0100, Conor Dooley wrote:
> > > On Wed, May 21, 2025 at 12:39:50PM -0600, Tom Rini wrote:
> > > > On Wed, 21 May 2025 17:50:03 +0800, Leo Li
On 08:45-20250522, Tom Rini wrote:
> On Thu, May 22, 2025 at 12:48:28PM +0530, Beleswar Padhi wrote:
>
> > Previously, MCU R5F runs in lockstep mode. Enable split-mode on MCU R5F
> > as the support to shut down core1 and use it for loading other firmware,
> > while DM
On Thu, May 22, 2025 at 08:45:59AM -0600, Tom Rini wrote:
> On Thu, May 22, 2025 at 12:28:18PM +0100, Conor Dooley wrote:
> > On Wed, May 21, 2025 at 12:39:50PM -0600, Tom Rini wrote:
> > > On Wed, 21 May 2025 17:50:03 +0800, Leo Liang wrote:
> > >
> > > > The following changes since commit
> > >
The usage of fdt_fixup_reserved is repeated for ATF and OP-TEE for
multiple platforms, this patch creates a single fdt API for fixing up
the reserved-memory node with added error handling.
All k3 platforms already share a common tispl template which ensures
binaries are loaded as per the respectiv
This clears UHS_MODE_SELECT for timing modes <= MMC_HS_52.
When initializing to HS400 mode, the host controller downgrades to non-uhs
modes so clear UHS_MODE_SELECT at modes <= MMC_HS_52.
This fixes eMMC writes on j7200 EVM.
Fixes: 6067aa66b3bb ("mmc: am654_sdhci: Add am654_sdhci_set_control_reg
From: Eoin Dickson
Add GPIO banks 0, 1 and 2 to the beaglev_fire device tree
Signed-off-by: Eoin Dickson
---
arch/riscv/dts/mpfs-beaglev-fire.dts | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/dts/mpfs-beaglev-fire.dts
b/arch/riscv/
From: Eoin Dickson
This series add SD card support for the Beagle-V-Fire. The Beagle-V-Fire uses
the
Microchip coreqspi xfer function and a gpio chip select, so this series adds
gpio
support for PolarFire SoC and the xfer function into the Microchip coreqspi
driver.
Eoin Dickson (4):
gpio:
From: Eoin Dickson
This driver adds GPIO support for PolarFire SoC family, this is required
to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects
Signed-off-by: Eoin Dickson
---
drivers/gpio/Kconfig | 6 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/mpfs_gpio.c | 1
From: Eoin Dickson
Enable CONFIG_MPFS_GPIO, CONFIG_CMD_GPIO and CONFIG_DM_GPIO and
CONFIG_MMC_SPI in the beaglev_fire_defconfig.
Signed-off-by: Eoin Dickson
---
configs/beaglev_fire_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/beaglev_fire_defconfig b/configs/beagl
From: Eoin Dickson
Add xfer function to PolarFire SoC coreqspi driver. The read and write
operations are limited to one byte at a time instead of four as CMD18
(multiple block read) reads garbage when four byte ops are enabled.
Signed-off-by: Eoin Dickson
---
drivers/spi/microchip_coreqspi.c |
On Thu, May 22, 2025 at 12:28:18PM +0100, Conor Dooley wrote:
> On Wed, May 21, 2025 at 12:39:50PM -0600, Tom Rini wrote:
> > On Wed, 21 May 2025 17:50:03 +0800, Leo Liang wrote:
> >
> > > The following changes since commit
> > > a3e09b24ffd4429909604f1b28455b44306edbaa:
> > >
> > > Merge tag
On Thu, May 22, 2025 at 12:48:28PM +0530, Beleswar Padhi wrote:
> Previously, MCU R5F runs in lockstep mode. Enable split-mode on MCU R5F
> as the support to shut down core1 and use it for loading other firmware,
> while DM runs on core0, has been added.
>
> Signed-off-by: Beleswar Padhi
> ---
>
On Thu, May 22, 2025 at 02:37:07PM +0200, Neil Armstrong wrote:
> From: Dmitrii Merkurev
>
> 1. Get partition info/size
> 2. Erase partition
> 3. Flash partition
> 4. BCB
>
> Signed-off-by: Dmitrii Merkurev
> Reviewed-by: Mattijs Korpershoek
> Tested-by: Mattijs Korpershoek
> Signed-off-by:
On 22/05/2025 15:09, Eoin Dickson wrote:
> From: Eoin Dickson
>
> This series add SD card support for the Beagle-V-Fire. The Beagle-V-Fire uses
> the
> Microchip coreqspi xfer function and a gpio chip select, so this series adds
> gpio
> support for PolarFire SoC and the xfer function into the
On Thu, May 22, 2025 at 02:37:06PM +0200, Neil Armstrong wrote:
> From: Dmitrii Merkurev
>
> Switch the mmc backend to this new shared block helpers,
> reducing block logic and only leaving MMC specific logic.
>
> Signed-off-by: Dmitrii Merkurev
> Reviewed-by: Mattijs Korpershoek
> Tested-by:
On Thu, May 22, 2025 at 09:52:30AM +0200, neil.armstr...@linaro.org wrote:
> On 22/05/2025 08:58, Mattijs Korpershoek wrote:
> > Hi Tom,
> >
> > On mer., mai 21, 2025 at 13:03, Tom Rini wrote:
> >
> > > On Wed, May 21, 2025 at 08:52:41PM +0200, Mattijs Korpershoek wrote:
> > > > Hi Tom,
> > > >
On Thu, 22 May 2025 at 02:01, Tom Rini wrote:
>
> In include/efi_loader.h we do not directly need , ,
> nor so remove them. In include/efi_tcg2.h
> we make use of but did not include it, so add it directly.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Heinrich Schuchardt
> Cc: Ilias Apalodimas
>
On Tue, May 20, 2025 at 5:55 AM Dario Binacchi
wrote:
>
> Commits [1] and [2] broke the booting of the BSH SMM S2 board. The
> patches in this series restore proper booting.
>
> [1] 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options")
> [2] dda454e933c6 ("serial: mxc: Support bulk enabling
On Wed, May 21, 2025 at 6:58 AM Dario Binacchi
wrote:
>
> From: Michael Trimarchi
>
> When using SPL on i.mx6 we frequently notice some DDR initialization
> mismatches between the SPL code and the non-SPL code.
>
> As the non-SPL code have been tested for long time and proves to be
> reliable, le
On Tue, May 20, 2025 at 6:02 AM Dario Binacchi
wrote:
>
> From: Michael Trimarchi
>
> Now that the UART driver can enable the required clocks, remove
> the hard-coded clock enable.
>
> Signed-off-by: Michael Trimarchi
> Signed-off-by: Dario Binacchi
Applied, thanks.
On Fri, May 16, 2025 at 7:46 AM Primoz Fiser wrote:
>
> Migrate to OF_UPSTREAM for phyCORE-i.MX93 since board can use upstream
> Linux kernel device-tree for phyBOARD-Segin-i.MX93.
>
> Signed-off-by: Primoz Fiser
Applied, thanks.
On Fri, May 16, 2025 at 5:17 AM Michael Trimarchi
wrote:
>
> The node is specified on the parent architecture u-boot.dtsi
> file
>
> Signed-off-by: Michael Trimarchi
Applied the series, thanks.
On Thu, May 15, 2025 at 12:10 PM Dario Binacchi
wrote:
>
> From: Michael Trimarchi
>
> The function arch_spl_mmc_get_uboot_raw_sector() was never compiled,
> even when the option CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION was
> enabled. So rename the macro SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTIT
:
https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
tags/u-boot-imx-master-20250522
for you to fetch changes up to 159b6f0e119962ce5da645f548cefe9196c8778e:
caam: Fix CAAM error on startup (2025-05-22 09:01:51 -0300)
u-boot-imx-master-20250522
--
CI: https://sour
This serie permits using any block device as target
for fastboot by moving the generic block logic into
a common set of helpers and also use them as generic
backend.
The erase logic has been extended to support software
erase since only 2 block drivers exposes the erase
operation.
Tests are welco
From: Dmitrii Merkurev
Switch the mmc backend to this new shared block helpers,
reducing block logic and only leaving MMC specific logic.
Signed-off-by: Dmitrii Merkurev
Reviewed-by: Mattijs Korpershoek
Tested-by: Mattijs Korpershoek
Signed-off-by: Neil Armstrong
---
drivers/fastboot/Kconfi
From: Dmitrii Merkurev
1. Get partition info/size
2. Erase partition
3. Flash partition
4. BCB
Signed-off-by: Dmitrii Merkurev
Reviewed-by: Mattijs Korpershoek
Tested-by: Mattijs Korpershoek
Signed-off-by: Neil Armstrong
---
drivers/fastboot/Kconfig | 29 +
From: Dmitrii Merkurev
Introduce fastboot block flashing functions and helpers
to be shared with the MMC implementation.
The write logic comes from the mmc implementation, while
the partition lookup is much simpler and could be extended.
For the erase logic, allmost no block drivers exposes the
board_init_f for the am62a is missing the call to spl_enable_cache which
exists for all other am62 platforms (check am625_init.c &
am62p5_init.c).
This allows the usage of caches while loading and parsing the u-boot.img
FIT resulting in ~2x speedup in the A53 SPL stage.
Signed-off-by: Anshul Dala
On May 22, 2025 11:03:33 AM GMT+02:00, Michal Simek
wrote:
>
>
>On 5/22/25 10:17, Rutherther wrote:
>> Michal Simek writes:
>>
>>> On 5/21/25 20:16, Rutherther wrote:
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.
This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used
Michal Simek writes:
> On 5/21/25 20:16, Rutherther wrote:
>> The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
>> four bits for each GEM, and one bit reserved in between.
>>
>> This has caused that using more than one GEM is impossible,
>> additionally corrupting the GEM0's
On Wed, May 21, 2025 at 12:39:50PM -0600, Tom Rini wrote:
> On Wed, 21 May 2025 17:50:03 +0800, Leo Liang wrote:
>
> > The following changes since commit a3e09b24ffd4429909604f1b28455b44306edbaa:
> >
> > Merge tag 'mmc-2025-05-20' of
> > https://source.denx.de/u-boot/custodians/u-boot-mmc (202
Hi Balaji,
On 5/21/25 10:44, Balaji Selvanathan wrote:
Introducing documentation support for Qualcomm Dragonwing series
boards. Documents the build and flashing steps.
Thanks for adding this!
Signed-off-by: Balaji Selvanathan
---
v3:
- No changes to this patch in v3
v2:
- This file is new
Please update the commit title, "qcom_qcs8300_defconfig"
Kind regards,
On 5/21/25 10:44, Balaji Selvanathan wrote:
Introduce a defconfig for QCS8300 based boards.
Signed-off-by: Balaji Selvanathan
---
v3:
- No changes to this patch in v3
v2:
- Renamed from "qcs8300_defconfig" to "qcom_qcs830
Hi,
On 5/21/25 14:27, Antonio Borneo wrote:
From: Patrice Chotard
The STM32MP2 boards have watchdog started by a previous boot
why only for STM32MP2...
I think it is case for STM32MP1 also.
and in the patch it is the case => default n for ARCH_STM32MP
= all STM32 MPU: STM32MP1(ARMv7) & S
Hi Neha,
On 22/05/25 13:21, Neha Malcom Francis wrote:
> On 22/05/25 12:48, Beleswar Padhi wrote:
>> During boot, ROM can bring up the MCU R5F cores in either lockstep or
>> split mode based on X509 certificate flags. If booted in split mode,
>> core 0 will run DM firmware and second core sits in
On 5/22/25 10:17, Rutherther wrote:
Michal Simek writes:
On 5/21/25 20:16, Rutherther wrote:
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.
This has caused that using more than one GEM is impossible,
addition
On 22/05/2025 08:58, Mattijs Korpershoek wrote:
Hi Tom,
On mer., mai 21, 2025 at 13:03, Tom Rini wrote:
On Wed, May 21, 2025 at 08:52:41PM +0200, Mattijs Korpershoek wrote:
Hi Tom,
On mer., mai 21, 2025 at 09:12, Tom Rini wrote:
On Wed, May 21, 2025 at 04:49:35PM +0200, Mattijs Korpersho
On 22/05/25 12:48, Beleswar Padhi wrote:
> Set boot core-opts to enable split mode for MCU R5 cluster by default.
>
> Signed-off-by: Beleswar Padhi
> ---
> arch/arm/dts/k3-j7200-binman.dtsi | 3 +++
> arch/arm/dts/k3-j721e-binman.dtsi | 4
> arch/arm/dts/k3-j721s2-binman.dtsi | 3 +++
> a
On 22/05/25 12:48, Beleswar Padhi wrote:
> Link the default firmware in the environment variable for MCU R5 core1
> for all J7 platforms.
>
> Signed-off-by: Beleswar Padhi
> ---
> board/ti/j7200/j7200.env | 2 +-
> board/ti/j721e/j721e.env | 2 +-
> board/ti/j721s2/j721s2.env | 2 +-
> board
On 22/05/25 12:48, Beleswar Padhi wrote:
> Acquire processor control before doing core reset operations in probe
> routine. Release the control afterwards, so that it can be acquired
> during core loading operations.
>
> Signed-off-by: Beleswar Padhi
> ---
> drivers/remoteproc/ti_k3_r5f_rproc.c
On 22/05/25 12:48, Beleswar Padhi wrote:
> During boot, ROM can bring up the MCU R5F cores in either lockstep or
> split mode based on X509 certificate flags. If booted in split mode,
> core 0 will run DM firmware and second core sits in WFI. Add support to
> shut down core 1 so that other firmware
Hi Beleswar
On 22/05/25 12:48, Beleswar Padhi wrote:
> Currently the MCU R5 processor ids and device ids are only defined for
> R5 SPL Stage. Expose these ids always so that A72 SPL can utilize this
> information to shutdown MCU R5 Core 1 when booted in Split mode.
>
> Signed-off-by: Beleswar Pad
Previously, MCU R5F runs in lockstep mode. Enable split-mode on MCU R5F
as the support to shut down core1 and use it for loading other firmware,
while DM runs on core0, has been added.
Signed-off-by: Beleswar Padhi
---
dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi | 2 +-
dts/u
Please do not merge this patch.
On 22/05/25 12:48, Beleswar Padhi wrote:
> Previously, MCU R5F runs in lockstep mode. Enable split-mode on MCU R5F
> as the support to shut down core1 and use it for loading other firmware,
> while DM runs on core0, has been added.
>
> Signed-off-by: Beleswar Padhi
Currently the MCU R5 processor ids and device ids are only defined for
R5 SPL Stage. Expose these ids always so that A72 SPL can utilize this
information to shutdown MCU R5 Core 1 when booted in Split mode.
Signed-off-by: Beleswar Padhi
---
arch/arm/mach-k3/include/mach/am62_hardware.h | 4 ++-
This series adds remoteproc support on MCU R5F in Split mode.
During boot, ROM can bring up the boot R5F cores in either lockstep or
split mode based on X509 certificate flags. If booted in lockstep mode,
the MCU R5F cores will run first the R5 SPL, and then once A72 comes up,
will run the Device
Set boot core-opts to enable split mode for MCU R5 cluster by default.
Signed-off-by: Beleswar Padhi
---
arch/arm/dts/k3-j7200-binman.dtsi | 3 +++
arch/arm/dts/k3-j721e-binman.dtsi | 4
arch/arm/dts/k3-j721s2-binman.dtsi | 3 +++
arch/arm/dts/k3-j784s4-binman.dtsi | 3 +++
4 files change
Link the default firmware in the environment variable for MCU R5 core1
for all J7 platforms.
Signed-off-by: Beleswar Padhi
---
board/ti/j7200/j7200.env | 2 +-
board/ti/j721e/j721e.env | 2 +-
board/ti/j721s2/j721s2.env | 2 +-
board/ti/j784s4/j784s4.env | 4 ++--
4 files changed, 5 insertio
Acquire processor control before doing core reset operations in probe
routine. Release the control afterwards, so that it can be acquired
during core loading operations.
Signed-off-by: Beleswar Padhi
---
drivers/remoteproc/ti_k3_r5f_rproc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
During boot, ROM can bring up the MCU R5F cores in either lockstep or
split mode based on X509 certificate flags. If booted in split mode,
core 0 will run DM firmware and second core sits in WFI. Add support to
shut down core 1 so that other firmwares can later be loaded on them.
The shutdown of M
On 5/21/25 15:41, Patrice Chotard wrote:
From: Gabriel Fernandez
Implement STM32MP25 reset drivers using stm32-core-reset API.
This reset stm32-reset-core API and will be able to use DT binding
index started from 0.
This patch also moves legacy reset into stm32 directory reset.
Signed-off-b
On 5/21/25 15:41, Patrice Chotard wrote:
From: Gabriel Fernandez
Add clock driver support for STM32MP25 SoCs.
Signed-off-by: Gabriel Fernandez
Signed-off-by: Valentin Caron
Signed-off-by: Patrice Chotard
Cc: Lukasz Majewski
Cc: Sean Anderson
---
drivers/clk/stm32/Kconfig |
Hi Tom,
Thank you for the patch.
On mer., mai 21, 2025 at 16:51, Tom Rini wrote:
> This file does not need a forward declaration of 'struct list_head' as
> it includes so remove it.
>
> Signed-off-by: Tom Rini
Reviewed-by: Mattijs Korpershoek
> ---
> Cc: Mattijs Korpershoek
> ---
> inclu
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